Moved common techlib files to techlibs/common

tests/i2c_bench/run-test.sh

@@ -27,8 +27,8 @@ EOT
 ./testbench_ref -tclbatch testbench_ref.tcl
 
 vlogcomp --work syn i2c_master_syn.v
-vlogcomp --work syn ../../techlibs/simlib.v
-vlogcomp --work syn ../../techlibs/stdcells_sim.v
+vlogcomp --work syn ../../techlibs/common/simlib.v
+vlogcomp --work syn ../../techlibs/common/stdcells_sim.v
 vlogcomp --work syn i2c_slave_model.v
 vlogcomp --work syn spi_slave_model.v
 vlogcomp --work syn tst_bench_top.v

tests/tools/autotest.sh

@@ -130,8 +130,8 @@ do
 			"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
 			compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
 					${bn}_tb.v ${bn}_syn${test_count}.v $libs \
-					"$toolsdir"/../../techlibs/simlib.v \
-					"$toolsdir"/../../techlibs/stdcells_sim.v
+					"$toolsdir"/../../techlibs/common/simlib.v \
+					"$toolsdir"/../../techlibs/common/stdcells_sim.v
 			if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
 			$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
 			test_count=$(( test_count + 1 ))

tests/tools/rtlview.sh

@@ -11,7 +11,7 @@ prjdir="$(dirname $0)/rtlview.tmp"
 mkdir -p "$prjdir"
 
 cp "$1" "$prjdir"/schematic.v
-cp "$(dirname $0)"/../../techlibs/blackbox.v "$prjdir"/blackbox.v
+cp "$(dirname $0)"/../../techlibs/common/blackbox.v "$prjdir"/blackbox.v
 cd "$prjdir"
 
 if fuser -s ise.out; then