mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 04:01:25 +00:00
Code Activity

Moved common techlib files to techlibs/common

Browse source
This commit is contained in:
Clifford Wolf 2013-09-15 11:52:57 +02:00
parent 647c23b7b7
commit 288ba9618a
13 changed files with 17 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

4
manual/CHAPTER_CellLib.tex
View file

@ -22,7 +22,7 @@ Note that all RTL cells have parameters indicating the size of inputs and output
passes modify RTL cells they must always keep the values of these parameters in sync with
the size of the signals connected to the inputs and outputs.
Simulation models for the RTL cells can be found in the file {\tt techlibs/simlib.v} in the Yosys
Simulation models for the RTL cells can be found in the file {\tt techlibs/common/simlib.v} in the Yosys
source tree.
\subsection{Unary Operators}
@ -347,7 +347,7 @@ Add a brief description of the {\tt \$fsm} cell type.
For gate level logic networks, fixed function single bit cells are used that do
not provide any parameters.
Simulation models for these cells can be found in the file {\tt techlibs/stdcells\_sim.v} in the Yosys
Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys
source tree.
\begin{table}[t]

2
manual/CHAPTER_Techmap.tex
View file

@ -27,7 +27,7 @@ cells with the provided implementation.
When no map file is provided, {\tt techmap} uses a built-in map file that
maps the Yosys RTL cell types to the internal gate library used by Yosys.
The curious reader may find this map file as {\tt techlibs/stdcells.v} in
The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in
the Yosys source tree.
Additional features have been added to {\tt techmap} to allow for conditional