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Cleaned tests

This commit is contained in:
Miodrag Milanovic 2019-10-04 12:42:06 +02:00
parent f94dc2c072
commit 286a272872
5 changed files with 4 additions and 49 deletions

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@ -1,12 +1,12 @@
read_verilog fsm.v
hierarchy -top top
hierarchy -top fsm
proc
flatten
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 6 t:EFX_FF