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Cleaned tests
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5 changed files with 4 additions and 49 deletions
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@ -1,12 +1,12 @@
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read_verilog fsm.v
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hierarchy -top top
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hierarchy -top fsm
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proc
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flatten
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#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
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#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 6 t:EFX_FF
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