mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
Add opt_ffinv pass.
This commit is contained in:
parent
f56a3bd48f
commit
2858bb03cd
4 changed files with 268 additions and 3 deletions
13
kernel/ff.cc
13
kernel/ff.cc
|
@ -669,14 +669,12 @@ namespace {
|
|||
}
|
||||
}
|
||||
|
||||
void FfData::flip_bits(const pool<int> &bits) {
|
||||
void FfData::flip_rst_bits(const pool<int> &bits) {
|
||||
if (!bits.size())
|
||||
return;
|
||||
|
||||
remove_init();
|
||||
|
||||
Wire *new_q = module->addWire(NEW_ID, width);
|
||||
|
||||
for (auto bit: bits) {
|
||||
if (has_arst)
|
||||
val_arst[bit] = invert(val_arst[bit]);
|
||||
|
@ -684,6 +682,15 @@ void FfData::flip_bits(const pool<int> &bits) {
|
|||
val_srst[bit] = invert(val_srst[bit]);
|
||||
val_init[bit] = invert(val_init[bit]);
|
||||
}
|
||||
}
|
||||
|
||||
void FfData::flip_bits(const pool<int> &bits) {
|
||||
if (!bits.size())
|
||||
return;
|
||||
|
||||
flip_rst_bits(bits);
|
||||
|
||||
Wire *new_q = module->addWire(NEW_ID, width);
|
||||
|
||||
if (has_sr && cell) {
|
||||
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
|
||||
|
|
|
@ -209,6 +209,8 @@ struct FfData {
|
|||
// inputs and output, flip the corresponding init/reset bits, swap clr/set
|
||||
// inputs with proper priority fix.
|
||||
void flip_bits(const pool<int> &bits);
|
||||
|
||||
void flip_rst_bits(const pool<int> &bits);
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue