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https://github.com/YosysHQ/yosys
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Merge from upstream
This commit is contained in:
Akash Levy
commit
283faf3bf9
9 changed files with 242 additions and 20 deletions
57
tests/proc/case_attr.ys
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57
tests/proc/case_attr.ys
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@ -0,0 +1,57 @@
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read_verilog -sv << EOF
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module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
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always @* begin
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W = F;
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(* full_case *)
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case (C)
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A: W = D;
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B: W = E;
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endcase
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end
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always @* begin
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X = F;
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case (C)
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A: X = D;
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B: X = E;
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endcase
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end
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always @* begin
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Y = F;
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(* full_case, parallel_case *)
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case (C)
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A: Y = D;
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B: Y = E;
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endcase
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end
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always @* begin
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Z = F;
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(* parallel_case *)
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case (C)
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A: Z = D;
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B: Z = E;
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endcase
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end
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endmodule
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EOF
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prep
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# For the ones which use full_case, the F signal shouldn't be included in
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# the input cone of W and Y.
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select -set full o:W o:Y %u %ci*
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select -assert-none i:F @full %i
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select -assert-count 1 o:X %ci* i:F %i
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select -assert-count 1 o:Z %ci* i:F %i
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# And for parallel_case there should be 1 $pmux compared to the 2 $mux
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# cells without.
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select -assert-none o:W %ci* t:$pmux %i
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select -assert-none o:X %ci* t:$pmux %i
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select -assert-count 1 o:Y %ci* t:$pmux %i
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select -assert-count 1 o:Z %ci* t:$pmux %i
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select -assert-count 2 o:W %ci* t:$mux %i
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select -assert-count 2 o:X %ci* t:$mux %i
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select -assert-none o:Y %ci* t:$mux %i
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select -assert-none o:Z %ci* t:$mux %i
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32
tests/various/splitnets.ys
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32
tests/various/splitnets.ys
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@ -0,0 +1,32 @@
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read_verilog <<EOT
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module test_module (
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a,
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b,
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x,
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y
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);
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input [0:0] a;
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output [0:0] b;
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input [1:0] x;
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output [1:0] y;
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assign b = a;
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assign y = x;
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endmodule
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EOT
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proc
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splitnets -ports -format __:
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select -assert-count 0 w:a;
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select -assert-count 1 w:a_0_;
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select -assert-count 0 w:a_1_;
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select -assert-count 0 w:b;
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select -assert-count 1 w:b_0_;
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select -assert-count 0 w:b_1_;
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select -assert-count 0 w:x;
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select -assert-count 1 w:x_0_;
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select -assert-count 1 w:x_1_;
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select -assert-count 0 w:y;
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select -assert-count 1 w:y_0_;
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select -assert-count 1 w:y_1_;
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54
tests/verilog/unique_priority_case.ys
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54
tests/verilog/unique_priority_case.ys
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@ -0,0 +1,54 @@
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read_verilog -sv << EOF
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module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
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always_comb begin
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W = F;
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priority case (C)
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A: W = D;
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B: W = E;
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endcase
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end
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always_comb begin
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X = F;
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case (C)
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A: X = D;
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B: X = E;
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endcase
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end
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always_comb begin
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Y = F;
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unique case (C)
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A: Y = D;
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B: Y = E;
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endcase
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end
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always_comb begin
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Z = F;
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unique0 case (C)
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A: Z = D;
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B: Z = E;
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endcase
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end
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endmodule
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EOF
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prep
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# For the ones which use priority/unique, the F signal shouldn't be included in
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# the input cone of W and Y.
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select -set full o:W o:Y %u %ci*
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select -assert-none i:F @full %i
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select -assert-count 1 o:X %ci* i:F %i
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select -assert-count 1 o:Z %ci* i:F %i
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# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
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# cells without.
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select -assert-none o:W %ci* t:$pmux %i
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select -assert-none o:X %ci* t:$pmux %i
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select -assert-count 1 o:Y %ci* t:$pmux %i
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select -assert-count 1 o:Z %ci* t:$pmux %i
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select -assert-count 2 o:W %ci* t:$mux %i
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select -assert-count 2 o:X %ci* t:$mux %i
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select -assert-none o:Y %ci* t:$mux %i
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select -assert-none o:Z %ci* t:$mux %i
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54
tests/verilog/unique_priority_if.ys
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54
tests/verilog/unique_priority_if.ys
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@ -0,0 +1,54 @@
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read_verilog -sv << EOF
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module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
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always_comb begin
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W = F;
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priority if (C == A)
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W = D;
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else if (C == B)
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W = E;
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end
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always_comb begin
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X = F;
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if (C == A)
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X = D;
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else if (C == B)
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X = E;
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end
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always_comb begin
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Y = F;
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unique if (C == A)
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Y = D;
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else if (C == B)
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Y = E;
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end
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always_comb begin
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Z = F;
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unique0 if (C == A)
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Z = D;
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else if (C == B)
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Z = E;
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end
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endmodule
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EOF
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prep
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# For the ones which use priority/unique, the F signal shouldn't be included in
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# the input cone of W and Y.
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select -set full o:W o:Y %u %ci*
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select -assert-none i:F @full %i
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select -assert-count 1 o:X %ci* i:F %i
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select -assert-count 1 o:Z %ci* i:F %i
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# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
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# cells without.
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select -assert-none o:W %ci* t:$pmux %i
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select -assert-none o:X %ci* t:$pmux %i
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select -assert-count 1 o:Y %ci* t:$pmux %i
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select -assert-count 1 o:Z %ci* t:$pmux %i
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select -assert-count 2 o:W %ci* t:$mux %i
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select -assert-count 2 o:X %ci* t:$mux %i
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select -assert-none o:Y %ci* t:$mux %i
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select -assert-none o:Z %ci* t:$mux %i
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