mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Fix spacing in opt_share tests, change wording in opt_share help

Browse source
This commit is contained in:
Bogdan Vukobratovic 2019-08-03 12:28:46 +02:00
parent c075486c59
commit 280c4e7794
11 changed files with 160 additions and 161 deletions
Download patch file Download diff file Expand all files Collapse all files

16
passes/opt/opt_share.cc
View file

@ -2,6 +2,7 @@
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* 2019 Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
* *
* Permission to use, copy, modify, and/or distribute this software for any * Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above * purpose with or without fee is hereby granted, provided that the above
@ -308,17 +309,20 @@ void remove_multi_user_outbits(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL:
} }
} }
struct OptRmdffPass : public Pass { struct OptSharePass : public Pass {
OptRmdffPass() : Pass("opt_share", "merge arithmetic operators that share an operand") {} OptSharePass() : Pass("opt_share", "merge arithmetic operators that share an operand") {}
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" opt_share [selection]\n"); log(" opt_share [selection]\n");
log("\n"); log("\n");
log("This pass identifies arithmetic operators that share an operand and whose\n");
log("results are used in mutually exclusive cases controlled by a multiplexer,\n"); log("This pass identifies mutually exclusive $alu arithmetic cells that:\n");
log("and merges them together by multiplexing the other operands.\n"); log(" (a) share an input operand\n");
log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell allowing\n");
log(" the $alu cell to be merged and the multiplexer to be moved from\n");
log(" multiplexing its output to multiplexing the non-shared input operands.\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
@ -454,6 +458,6 @@ struct OptRmdffPass : public Pass {
} }
} }
} OptRmdffPass; } OptSharePass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END

12
tests/opt/opt_share_add_sub.v
View file

@ -1,10 +1,10 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input sel, input sel,
output [15:0] res, output [15:0] res,
); );
assign res = {sel ? a + b : a - b}; assign res = {sel ? a + b : a - b};
endmodule endmodule

20
tests/opt/opt_share_cat.v
View file

@ -1,15 +1,15 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input sel, input sel,
output [63:0] res, output [63:0] res,
); );
reg [31: 0] cat1 = {a+b, c+d}; reg [31: 0] cat1 = {a+b, c+d};
reg [31: 0] cat2 = {a-b, c-d}; reg [31: 0] cat2 = {a-b, c-d};
assign res = {b, sel ? cat1 : cat2, a}; assign res = {b, sel ? cat1 : cat2, a};
endmodule endmodule

34
tests/opt/opt_share_cat_multiuser.v
View file

@ -1,22 +1,22 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input sel, input sel,
output reg [47:0] res, output reg [47:0] res,
); );
wire [15:0] add_res = a+b; wire [15:0] add_res = a+b;
wire [15:0] sub_res = a-b; wire [15:0] sub_res = a-b;
wire [31: 0] cat1 = {add_res, c+d}; wire [31: 0] cat1 = {add_res, c+d};
wire [31: 0] cat2 = {sub_res, c-d}; wire [31: 0] cat2 = {sub_res, c-d};
always @* begin always @* begin
case(sel) case(sel)
0: res = {cat1, add_res}; 0: res = {cat1, add_res};
1: res = {cat2, add_res}; 1: res = {cat2, add_res};
endcase endcase
end end
endmodule endmodule

32
tests/opt/opt_share_diff_port_widths.v
View file

@ -1,21 +1,21 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [1:0] sel, input [1:0] sel,
output reg [15:0] res output reg [15:0] res
); );
wire [15:0] add0_res = a+b; wire [15:0] add0_res = a+b;
wire [15:0] add1_res = a+c; wire [15:0] add1_res = a+c;
always @* begin always @* begin
case(sel) case(sel)
0: res = add0_res[10:0]; 0: res = add0_res[10:0];
1: res = add1_res[10:0]; 1: res = add1_res[10:0];
2: res = a - b; 2: res = a - b;
default: res = 32'bx; default: res = 32'bx;
endcase endcase
end end
endmodule endmodule

29
tests/opt/opt_share_extend.v
View file

@ -1,19 +1,18 @@
module opt_share_test( module opt_share_test(
input signed [7:0] a, input signed [7:0] a,
input signed [10:0] b, input signed [10:0] b,
input signed [15:0] c, input signed [15:0] c,
input [1:0] sel, input [1:0] sel,
output reg signed [15:0] res output reg signed [15:0] res
); );
always @* begin
always @* begin case(sel)
case(sel) 0: res = a + b;
0: res = a + b; 1: res = a - b;
1: res = a - b; 2: res = a + c;
2: res = a + c; default: res = 16'bx;
default: res = 16'bx; endcase
endcase end
end
endmodule endmodule

35
tests/opt/opt_share_large_pmux_cat.v
View file

@ -1,22 +1,21 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [2:0] sel, input [2:0] sel,
output reg [31:0] res output reg [31:0] res
); );
always @* begin
always @* begin case(sel)
case(sel) 0: res = {a + b, a};
0: res = {a + b, a}; 1: res = {a - b, b};
1: res = {a - b, b}; 2: res = {a + c, c};
2: res = {a + c, c}; 3: res = {a - c, a};
3: res = {a - c, a}; 4: res = {b, b};
4: res = {b, b}; 5: res = {c, c};
5: res = {c, c}; default: res = 32'bx;
default: res = 32'bx; endcase
endcase end
end
endmodule endmodule

40
tests/opt/opt_share_large_pmux_cat_multipart.v
View file

@ -1,25 +1,25 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input [2:0] sel, input [2:0] sel,
output reg [31:0] res output reg [31:0] res
); );
wire [15:0] add0_res = a+d; wire [15:0] add0_res = a+d;
always @* begin always @* begin
case(sel) case(sel)
0: res = {add0_res, a}; 0: res = {add0_res, a};
1: res = {a - b, add0_res[7], 15'b0}; 1: res = {a - b, add0_res[7], 15'b0};
2: res = {b-a, b}; 2: res = {b-a, b};
3: res = {d, b - c}; 3: res = {d, b - c};
4: res = {d, b - a}; 4: res = {d, b - a};
5: res = {c, d}; 5: res = {c, d};
6: res = {a - c, b-d}; 6: res = {a - c, b-d};
default: res = 32'bx; default: res = 32'bx;
endcase endcase
end end
endmodule endmodule

39
tests/opt/opt_share_large_pmux_multipart.v
View file

@ -1,24 +1,23 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [15:0] d, input [15:0] d,
input [2:0] sel, input [2:0] sel,
output reg [15:0] res output reg [15:0] res
); );
always @* begin
always @* begin case(sel)
case(sel) 0: res = a + d;
0: res = a + d; 1: res = a - b;
1: res = a - b; 2: res = b;
2: res = b; 3: res = b - c;
3: res = b - c; 4: res = b - a;
4: res = b - a; 5: res = c;
5: res = c; 6: res = a - c;
6: res = a - c; default: res = 16'bx;
default: res = 16'bx; endcase
endcase end
end
endmodule endmodule

35
tests/opt/opt_share_large_pmux_part.v
View file

@ -1,22 +1,21 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [2:0] sel, input [2:0] sel,
output reg [15:0] res output reg [15:0] res
); );
always @* begin
always @* begin case(sel)
case(sel) 0: res = a + b;
0: res = a + b; 1: res = a - b;
1: res = a - b; 2: res = a + c;
2: res = a + c; 3: res = a - c;
3: res = a - c; 4: res = b;
4: res = b; 5: res = c;
5: res = c; default: res = 16'bx;
default: res = 16'bx; endcase
endcase end
end
endmodule endmodule

29
tests/opt/opt_share_mux_tree.v
View file

@ -1,19 +1,18 @@
module opt_share_test( module opt_share_test(
input [15:0] a, input [15:0] a,
input [15:0] b, input [15:0] b,
input [15:0] c, input [15:0] c,
input [1:0] sel, input [1:0] sel,
output reg [15:0] res output reg [15:0] res
); );
always @* begin
always @* begin case(sel)
case(sel) 0: res = a + b;
0: res = a + b; 1: res = a - b;
1: res = a - b; 2: res = a + c;
2: res = a + c; default: res = 16'bx;
default: res = 16'bx; endcase
endcase end
end
endmodule endmodule