mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-12 20:18:20 +00:00
Merge pull request #2574 from dh73/master
Accept disable case for SVA liveness properties.
This commit is contained in:
commit
27d7741540
|
@ -1759,6 +1759,11 @@ struct VerificSvaImporter
|
||||||
clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
|
clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// accept in disable case
|
||||||
|
|
||||||
|
if (clocking.disable_sig != State::S0)
|
||||||
|
sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig);
|
||||||
|
|
||||||
// generate fair/live cell
|
// generate fair/live cell
|
||||||
|
|
||||||
RTLIL::Cell *c = nullptr;
|
RTLIL::Cell *c = nullptr;
|
||||||
|
|
Loading…
Reference in a new issue