mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00
Code Activity

fmt: allow padding characters other than '0' and ' '.

Browse source 
When converted to Verilog, padding characters are replaced with one of
these two. Otherwise padding is performed with exactly that character.
This commit is contained in:
Catherine 2024-03-28 09:52:59 +00:00 committed by Marcelina Kościelnicka
parent ddf7b46955
commit 27cb4c52b4
1 changed files with 1 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
kernel/fmt.cc
View file

@ -91,10 +91,7 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
if (++i == fmt.size()) if (++i == fmt.size())
log_assert(false && "Unexpected end in format substitution"); log_assert(false && "Unexpected end in format substitution");
if (fmt[i] == '0' || fmt[i] == ' ') part.padding = fmt[i];
part.padding = fmt[i];
else
log_assert(false && "Unexpected padding in format substitution");
if (++i == fmt.size()) if (++i == fmt.size())
log_assert(false && "Unexpected end in format substitution"); log_assert(false && "Unexpected end in format substitution");
@ -550,7 +547,6 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
if (part.width == 0) { if (part.width == 0) {
fmt.str += '0'; fmt.str += '0';
} else if (part.width > 0) { } else if (part.width > 0) {
log_assert(part.padding == ' ' || part.padding == '0');
if (part.base != 10 || part.padding == '0') if (part.base != 10 || part.padding == '0')
fmt.str += '0'; fmt.str += '0';
fmt.str += std::to_string(part.width); fmt.str += std::to_string(part.width);
@ -576,7 +572,6 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
fmt.str += '-'; fmt.str += '-';
if (part.sig.size() == 8) { if (part.sig.size() == 8) {
if (part.width > 0) { if (part.width > 0) {
log_assert(part.padding == '0' || part.padding == ' ');
if (part.padding == '0') if (part.padding == '0')
fmt.str += part.padding; fmt.str += part.padding;
fmt.str += std::to_string(part.width); fmt.str += std::to_string(part.width);
@ -585,7 +580,6 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
} else { } else {
log_assert(part.sig.size() % 8 == 0); log_assert(part.sig.size() % 8 == 0);
if (part.width > 0) { if (part.width > 0) {
log_assert(part.padding == ' '); // no zero padding
fmt.str += std::to_string(part.width); fmt.str += std::to_string(part.width);
} }
fmt.str += 's'; fmt.str += 's';
@ -616,7 +610,6 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
fmt.str += '+'; fmt.str += '+';
if (part.justify == FmtPart::LEFT) if (part.justify == FmtPart::LEFT)
fmt.str += '-'; fmt.str += '-';
log_assert(part.padding == ' ' || part.padding == '0');
if (part.padding == '0' && part.width > 0) if (part.padding == '0' && part.width > 0)
fmt.str += '0'; fmt.str += '0';
fmt.str += std::to_string(part.width); fmt.str += std::to_string(part.width);