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Proper example code

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This commit is contained in:
Miodrag Milanovic 2022-03-14 15:39:11 +01:00
parent a502570c25
commit 27c5bafc95
2 changed files with 3 additions and 1 deletions
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2
tests/sat/ram_memory.v
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@ -27,6 +27,8 @@ module ram_memory(
store[256] <= 8'b11010001; // OUT [0],R1
store[257] <= 8'b00000000; //
store[258] <= 8'b01111110; // RET
store[512] <= 8'b00000000;
end
always @(posedge clk)