Docs: working on opt page

Replace leftover `opt` example source/images with examples specific to the `opt_*` pass.
Currently has images for `opt_expr`, `opt_merge`, `opt_muxtree`, and `opt_share`.
Also includes some other TODO updates.

docs/source/code_examples/synth_flow/Makefile

@@ -1,6 +1,5 @@
 
 TARGETS += proc_01 proc_02 proc_03
-TARGETS += opt_01 opt_02 opt_03 opt_04
 TARGETS += memory_01 memory_02
 TARGETS += techmap_01
 

docs/source/code_examples/synth_flow/opt_01.v

@@ -1,3 +0,0 @@
-module test(input A, B, output Y);
-assign Y = A ? A ? B : 1'b1 : B;
-endmodule

docs/source/code_examples/synth_flow/opt_01.ys

@@ -1,3 +0,0 @@
-read_verilog opt_01.v
-hierarchy -check -top test
-opt

docs/source/code_examples/synth_flow/opt_02.v

@@ -1,3 +0,0 @@
-module test(input A, output Y, Z);
-assign Y = A == A, Z = A != A;
-endmodule

docs/source/code_examples/synth_flow/opt_02.ys

@@ -1,3 +0,0 @@
-read_verilog opt_02.v
-hierarchy -check -top test
-opt

docs/source/code_examples/synth_flow/opt_03.v

@@ -1,4 +0,0 @@
-module test(input  [3:0] A, B,
-            output [3:0] Y, Z);
-assign Y = A + B, Z = B + A;
-endmodule

docs/source/code_examples/synth_flow/opt_03.ys

@@ -1,3 +0,0 @@
-read_verilog opt_03.v
-hierarchy -check -top test
-opt

docs/source/code_examples/synth_flow/opt_04.v

@@ -1,19 +0,0 @@
-module test(input CLK, ARST,
-            output [7:0] Q1, Q2, Q3);
-
-wire NO_CLK = 0;
-
-always @(posedge CLK, posedge ARST)
-	if (ARST)
-		Q1 <= 42;
-
-always @(posedge NO_CLK, posedge ARST)
-	if (ARST)
-		Q2 <= 42;
-	else
-		Q2 <= 23;
-
-always @(posedge CLK)
-	Q3 <= 42;
-
-endmodule

docs/source/code_examples/synth_flow/opt_04.ys

@@ -1,3 +0,0 @@
-read_verilog opt_04.v
-hierarchy -check -top test
-proc; opt