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Docs: working on opt page

Replace leftover `opt` example source/images with examples specific to the `opt_*` pass.
Currently has images for `opt_expr`, `opt_merge`, `opt_muxtree`, and `opt_share`.
Also includes some other TODO updates.
This commit is contained in:
Krystine Sherwin 2024-01-17 11:00:42 +13:00
parent 63a0f80996
commit 27ae093dba
No known key found for this signature in database
18 changed files with 140 additions and 105 deletions

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@ -0,0 +1,19 @@
PROGRAM_PREFIX :=
YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
DOT_NAMES = opt_share opt_muxtree opt_merge opt_expr
DOTS := $(addsuffix .dot,$(DOT_NAMES))
dots: $(DOTS)
%_full.dot: %.ys
$(YOSYS) $<
%.dot: %_full.dot
gvpack -u $*_full.dot -o $@
.PHONY: clean
clean:
rm -f *.dot

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read_verilog <<EOT
module uut(
input a,
output y, z
);
assign y = a == a;
assign z = a != a;
endmodule
EOT
copy uut after
opt_expr after
clean
show -format dot -prefix opt_expr_full -notitle -color cornflowerblue uut

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read_verilog <<EOT
module uut(
input [3:0] a, b,
output [3:0] y, z
);
assign y = a + b;
assign z = b + a;
endmodule
EOT
copy uut after
opt_merge after
clean
show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut

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read_verilog <<EOT
module uut(
input a, b, c, d,
output y
);
assign y = a ? (a ? b : c) : d;
endmodule
EOT
copy uut after
opt_muxtree after
clean
show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut

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read_verilog <<EOT
module uut(
input [15:0] a, b,
input sel,
output [15:0] res,
);
assign res = {sel ? a + b : a - b};
endmodule
EOT
copy uut after
opt_share after
clean
show -format dot -prefix opt_share_full -notitle -color cornflowerblue uut