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Added support for "upto" wires to Verilog front- and back-end

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This commit is contained in:
Clifford Wolf 2014-07-28 14:25:03 +02:00
parent 3c45277ee0
commit 27a872d1e7
6 changed files with 96 additions and 22 deletions
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4
frontends/ast/simplify.cc
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@ -504,6 +504,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_RANGE) {
bool old_range_valid = range_valid;
range_valid = false;
range_swapped = false;
range_left = -1;
range_right = 0;
log_assert(children.size() >= 1);
@ -525,6 +526,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
int tmp = range_right;
range_right = range_left;
range_left = tmp;
range_swapped = true;
}
}
@ -535,6 +537,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (!range_valid)
did_something = true;
range_valid = true;
range_swapped = children[0]->range_swapped;
range_left = children[0]->range_left;
range_right = children[0]->range_right;
}
@ -542,6 +545,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (!range_valid)
did_something = true;
range_valid = true;
range_swapped = false;
range_left = 0;
range_right = 0;
}