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Added support for "upto" wires to Verilog front- and back-end

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This commit is contained in:
Clifford Wolf 2014-07-28 14:25:03 +02:00
parent 3c45277ee0
commit 27a872d1e7
6 changed files with 96 additions and 22 deletions
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5
frontends/ast/ast.cc
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@ -181,6 +181,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
is_signed = false;
is_string = false;
range_valid = false;
range_swapped = false;
port_id = 0;
range_left = -1;
range_right = 0;
@ -276,7 +277,7 @@ void AstNode::dumpAst(FILE *f, std::string indent)
if (port_id > 0)
fprintf(f, " port=%d", port_id);
if (range_valid || range_left != -1 || range_right != 0)
fprintf(f, " range=[%d:%d]%s", range_left, range_right, range_valid ? "" : "!");
fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
if (integer != 0)
fprintf(f, " int=%u", (int)integer);
if (realvalue != 0)
@ -620,6 +621,8 @@ bool AstNode::operator==(const AstNode &other) const
return false;
if (range_valid != other.range_valid)
return false;
if (range_swapped != other.range_swapped)
return false;
if (port_id != other.port_id)
return false;
if (range_left != other.range_left)