mirror of
https://github.com/YosysHQ/yosys
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Run ABCs in parallel.
Large circuits can run hundreds or thousands of ABCs in a single AbcPass. For some circuits, some of those ABC runs can run for hundreds of seconds. Running ABCs in parallel with each other and in parallel with main-thread processing (reading and writing BLIF files, copying ABC BLIF output into the design) can give large speedups.
This commit is contained in:
Robert O'Callahan
Jannis Harder
parent
38f8165c80
commit
27462da208
6 changed files with 362 additions and 88 deletions
14
Makefile
14
Makefile
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@ -44,7 +44,12 @@ LINK_ABC := 0
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# Needed for environments that can't run executables (i.e. emscripten, wasm)
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DISABLE_SPAWN := 0
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# Needed for environments that don't have proper thread support (i.e. emscripten, wasm--for now)
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ENABLE_THREADS := 1
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ifeq ($(ENABLE_THREADS),1)
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DISABLE_ABC_THREADS := 0
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else
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DISABLE_ABC_THREADS := 1
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endif
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# clang sanitizers
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SANITIZER =
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@ -300,6 +305,7 @@ DISABLE_SPAWN := 1
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ifeq ($(ENABLE_ABC),1)
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LINK_ABC := 1
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ENABLE_THREADS := 0
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DISABLE_ABC_THREADS := 1
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endif
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@ -457,6 +463,11 @@ CXXFLAGS := -Og -DDEBUG $(filter-out $(OPT_LEVEL),$(CXXFLAGS))
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STRIP :=
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endif
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ifeq ($(ENABLE_THREADS),1)
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CXXFLAGS += -DYOSYS_ENABLE_THREADS
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LIBS += -lpthread
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endif
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ifeq ($(ENABLE_ABC),1)
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CXXFLAGS += -DYOSYS_ENABLE_ABC
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ifeq ($(LINK_ABC),1)
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@ -612,6 +623,7 @@ $(eval $(call add_include_file,kernel/satgen.h))
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$(eval $(call add_include_file,kernel/scopeinfo.h))
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$(eval $(call add_include_file,kernel/sexpr.h))
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$(eval $(call add_include_file,kernel/sigtools.h))
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$(eval $(call add_include_file,kernel/threading.h))
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$(eval $(call add_include_file,kernel/timinginfo.h))
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$(eval $(call add_include_file,kernel/utils.h))
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$(eval $(call add_include_file,kernel/yosys.h))
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@ -638,7 +650,7 @@ OBJS += kernel/log_compat.o
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endif
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OBJS += kernel/binding.o kernel/tclapi.o
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OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o
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OBJS += kernel/drivertools.o kernel/functional.o
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OBJS += kernel/drivertools.o kernel/functional.o kernel/threading.o
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ifeq ($(ENABLE_ZLIB),1)
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OBJS += kernel/fstdata.o
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endif
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45
kernel/threading.cc
Normal file
45
kernel/threading.cc
Normal file
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@ -0,0 +1,45 @@
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#include "kernel/yosys_common.h"
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#include "kernel/threading.h"
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YOSYS_NAMESPACE_BEGIN
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void DeferredLogs::flush()
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{
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for (auto &m : logs)
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if (m.error)
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YOSYS_NAMESPACE_PREFIX log_error("%s", m.text.c_str());
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else
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YOSYS_NAMESPACE_PREFIX log("%s", m.text.c_str());
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}
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int ThreadPool::pool_size(int reserved_cores, int max_threads)
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{
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#ifdef YOSYS_ENABLE_THREADS
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int num_threads = std::min<int>(std::thread::hardware_concurrency() - reserved_cores, max_threads);
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return std::max(0, num_threads);
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#else
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return 0;
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#endif
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}
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ThreadPool::ThreadPool(int pool_size, std::function<void(int)> b)
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: body(std::move(b))
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{
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#ifdef YOSYS_ENABLE_THREADS
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threads.reserve(pool_size);
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for (int i = 0; i < pool_size; i++)
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threads.emplace_back([i, this]{ body(i); });
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#else
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log_assert(pool_size == 0);
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#endif
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}
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ThreadPool::~ThreadPool()
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{
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#ifdef YOSYS_ENABLE_THREADS
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for (auto &t : threads)
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t.join();
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#endif
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}
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YOSYS_NAMESPACE_END
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159
kernel/threading.h
Normal file
159
kernel/threading.h
Normal file
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@ -0,0 +1,159 @@
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#include <deque>
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#ifdef YOSYS_ENABLE_THREADS
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#include <condition_variable>
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#include <mutex>
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#include <thread>
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#endif
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#include "kernel/yosys_common.h"
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#include "kernel/log.h"
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#ifndef YOSYS_THREADING_H
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#define YOSYS_THREADING_H
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YOSYS_NAMESPACE_BEGIN
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// Concurrent queue implementation. Not fast, but simple.
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// Multi-producer, multi-consumer, optionally bounded.
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// When YOSYS_ENABLE_THREADS is not defined, this is just a non-thread-safe non-blocking deque.
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template <typename T>
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class ConcurrentQueue
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{
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public:
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ConcurrentQueue(int capacity = INT_MAX)
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: capacity(capacity) {}
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// Push an element into the queue. If it's at capacity, block until there is room.
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void push_back(T t)
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{
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#ifdef YOSYS_ENABLE_THREADS
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std::unique_lock<std::mutex> lock(mutex);
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not_full_condition.wait(lock, [this] { return static_cast<int>(contents.size()) < capacity; });
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if (contents.empty())
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not_empty_condition.notify_one();
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#endif
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log_assert(!closed);
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contents.push_back(std::move(t));
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#ifdef YOSYS_ENABLE_THREADS
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if (static_cast<int>(contents.size()) < capacity)
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not_full_condition.notify_one();
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#endif
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}
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// Signal that no more elements will be produced. `pop_front()` will return nullopt.
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void close()
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{
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#ifdef YOSYS_ENABLE_THREADS
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std::unique_lock<std::mutex> lock(mutex);
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not_empty_condition.notify_all();
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#endif
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closed = true;
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}
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// Pop an element from the queue. Blocks until an element is available
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// or the queue is closed and empty.
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std::optional<T> pop_front()
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{
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return pop_front_internal(true);
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}
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// Pop an element from the queue. Does not block, just returns nullopt if the
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// queue is empty.
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std::optional<T> try_pop_front()
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{
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return pop_front_internal(false);
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}
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private:
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#ifdef YOSYS_ENABLE_THREADS
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std::optional<T> pop_front_internal(bool wait)
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{
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std::unique_lock<std::mutex> lock(mutex);
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if (wait) {
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not_empty_condition.wait(lock, [this] { return !contents.empty() || closed; });
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}
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#else
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std::optional<T> pop_front_internal(bool)
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{
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#endif
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if (contents.empty())
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return std::nullopt;
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#ifdef YOSYS_ENABLE_THREADS
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if (static_cast<int>(contents.size()) == capacity)
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not_full_condition.notify_one();
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#endif
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T result = std::move(contents.front());
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contents.pop_front();
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#ifdef YOSYS_ENABLE_THREADS
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if (!contents.empty())
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not_empty_condition.notify_one();
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#endif
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return std::move(result);
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}
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#ifdef YOSYS_ENABLE_THREADS
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std::mutex mutex;
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// Signals one waiter thread when the queue changes and is not full.
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std::condition_variable not_full_condition;
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// Signals one waiter thread when the queue changes and is not empty.
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std::condition_variable not_empty_condition;
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#endif
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std::deque<T> contents;
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int capacity;
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bool closed = false;
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};
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class DeferredLogs
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{
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public:
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template <typename... Args>
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void log(FmtString<TypeIdentity<Args>...> fmt, Args... args)
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{
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logs.push_back({fmt.format(args...), false});
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}
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template <typename... Args>
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void log_error(FmtString<TypeIdentity<Args>...> fmt, Args... args)
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{
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logs.push_back({fmt.format(args...), true});
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}
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void flush();
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private:
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struct Message
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{
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std::string text;
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bool error;
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};
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std::vector<Message> logs;
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};
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class ThreadPool
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{
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public:
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// Computes the number of worker threads to use.
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// `reserved_cores` cores are set aside for other threads (e.g. work on the main thread).
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// `max_threads` --- don't return more workers than this.
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// The result may be 0.
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static int pool_size(int reserved_cores, int max_threads);
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// Create a pool of threads running the given closure (parameterized by thread number).
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// `pool_size` must be the result of a `pool_size()` call.
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ThreadPool(int pool_size, std::function<void(int)> b);
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ThreadPool(ThreadPool &&other) = delete;
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// Waits for all threads to terminate. Make sure those closures return!
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~ThreadPool();
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// Return the number of threads in the pool.
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int num_threads() const
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{
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#ifdef YOSYS_ENABLE_THREADS
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return threads.size();
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#else
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return 0;
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#endif
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}
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private:
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std::function<void(int)> body;
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#ifdef YOSYS_ENABLE_THREADS
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std::vector<std::thread> threads;
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#endif
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};
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YOSYS_NAMESPACE_END
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#endif // YOSYS_THREADING_H
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@ -177,7 +177,7 @@ int run_command(const std::string &command, std::function<void(const std::string
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int ret = pclose(f);
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if (ret < 0)
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return -1;
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return -2;
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#ifdef _WIN32
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return ret;
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#else
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@ -38,6 +38,7 @@ popd
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} > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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sed -i 's,</AdditionalIncludeDirectories>,</AdditionalIncludeDirectories>\n <LanguageStandard>stdcpp17</LanguageStandard>\n <AdditionalOptions>/Zc:__cplusplus %(AdditionalOptions)</AdditionalOptions>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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sed -i 's,<PreprocessorDefinitions>,<PreprocessorDefinitions>YOSYS_ENABLE_THREADS;,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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if [ -f "/usr/include/FlexLexer.h" ] ; then
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sed -i 's,</AdditionalIncludeDirectories>,;..\\yosys\\libs\\flex</AdditionalIncludeDirectories>,g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new
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fi
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@ -48,6 +48,7 @@
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#include "kernel/ff.h"
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#include "kernel/cost.h"
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#include "kernel/log.h"
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#include "kernel/threading.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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@ -55,6 +56,7 @@
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#include <cerrno>
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#include <sstream>
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#include <climits>
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#include <memory>
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#include <vector>
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#ifndef _WIN32
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@ -153,30 +155,41 @@ struct AbcSigVal {
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using AbcSigMap = SigValMap<AbcSigVal>;
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struct AbcModuleState {
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// Used by off-main-threads. Contains no direct or indirect access to RTLIL.
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struct RunAbcState {
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const AbcConfig &config;
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int map_autoidx = 0;
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std::string tempdir_name;
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std::vector<gate_t> signal_list;
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bool did_run = false;
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bool err = false;
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DeferredLogs logs;
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dict<int, std::string> pi_map, po_map;
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RunAbcState(const AbcConfig &config) : config(config) {}
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void run();
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};
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struct AbcModuleState {
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RunAbcState run_abc;
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int map_autoidx = 0;
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std::vector<RTLIL::SigBit> signal_bits;
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dict<RTLIL::SigBit, int> signal_map;
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FfInitVals &initvals;
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bool had_init = false;
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bool did_run_abc = false;
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bool clk_polarity = false;
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bool en_polarity = false;
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bool arst_polarity = false;
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bool srst_polarity = false;
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RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
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dict<int, std::string> pi_map, po_map;
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int undef_bits_lost = 0;
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std::string tempdir_name;
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AbcModuleState(const AbcConfig &config, FfInitVals &initvals)
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: config(config), initvals(initvals) {}
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: run_abc(config), initvals(initvals) {}
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AbcModuleState(AbcModuleState&&) = delete;
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int map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
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void mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig);
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@ -186,7 +199,6 @@ struct AbcModuleState {
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void handle_loops(AbcSigMap &assign_map, RTLIL::Module *module);
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void prepare_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector<RTLIL::Cell*> &cells,
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bool dff_mode, std::string clk_str);
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void run_abc();
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void extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module);
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void finish();
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};
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@ -200,7 +212,7 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g
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if (signal_map.count(bit) == 0) {
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gate_t gate;
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gate.id = signal_list.size();
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gate.id = run_abc.signal_list.size();
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gate.type = G(NONE);
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gate.in1 = -1;
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gate.in2 = -1;
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@ -212,11 +224,11 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g
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gate.init = initvals(bit);
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gate.bit_str = std::string(log_signal(bit));
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signal_map[bit] = gate.id;
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signal_list.push_back(std::move(gate));
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run_abc.signal_list.push_back(std::move(gate));
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signal_bits.push_back(bit);
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}
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gate_t &gate = signal_list[signal_map[bit]];
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gate_t &gate = run_abc.signal_list[signal_map[bit]];
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if (gate_type != G(NONE))
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gate.type = gate_type;
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@ -236,7 +248,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig)
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{
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for (auto &bit : assign_map(sig))
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if (bit.wire != nullptr && signal_map.count(bit) > 0)
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signal_list[signal_map[bit]].is_port = true;
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run_abc.signal_list[signal_map[bit]].is_port = true;
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}
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bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
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@ -315,7 +327,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
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if (keepff) {
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SigBit bit = ff.sig_q;
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if (assign_map(bit).wire != nullptr) {
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signal_list[gate_id].is_port = true;
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run_abc.signal_list[gate_id].is_port = true;
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}
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if (bit.wire != nullptr)
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bit.wire->attributes[ID::keep] = 1;
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@ -467,7 +479,7 @@ std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **o
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size_t postfix_start = abc_sname.find_first_not_of("0123456789");
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std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
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if (sid < GetSize(signal_list))
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if (sid < GetSize(run_abc.signal_list))
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{
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const auto &bit = signal_bits.at(sid);
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if (bit.wire != nullptr)
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@ -507,7 +519,7 @@ void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edg
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}
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for (auto n : nodes)
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fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, signal_list[n].bit_str.c_str(),
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fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, run_abc.signal_list[n].bit_str.c_str(),
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n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
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for (auto &e : edges)
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@ -529,7 +541,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
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// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
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dict<int, pool<int>> edges;
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std::vector<int> in_edges_count(signal_list.size());
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std::vector<int> in_edges_count(run_abc.signal_list.size());
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pool<int> workpool;
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FILE *dot_f = nullptr;
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@ -538,7 +550,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
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// uncomment for troubleshooting the loop detection code
|
||||
// dot_f = fopen("test.dot", "w");
|
||||
|
||||
for (auto &g : signal_list) {
|
||||
for (auto &g : run_abc.signal_list) {
|
||||
if (g.type == G(NONE) || g.type == G(FF) || g.type == G(FF0) || g.type == G(FF1)) {
|
||||
workpool.insert(g.id);
|
||||
} else {
|
||||
|
|
@ -621,29 +633,29 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
|
|||
for (int id2 : edges[id1]) {
|
||||
if (first_line)
|
||||
log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
|
||||
signal_list[id1].bit_str, signal_list[id2].bit_str);
|
||||
run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str);
|
||||
else
|
||||
log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
|
||||
signal_list[id1].bit_str, signal_list[id2].bit_str);
|
||||
run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str);
|
||||
first_line = false;
|
||||
}
|
||||
|
||||
int id3 = map_signal(assign_map, RTLIL::SigSpec(wire));
|
||||
signal_list[id1].is_port = true;
|
||||
signal_list[id3].is_port = true;
|
||||
run_abc.signal_list[id1].is_port = true;
|
||||
run_abc.signal_list[id3].is_port = true;
|
||||
log_assert(id3 == int(in_edges_count.size()));
|
||||
in_edges_count.push_back(0);
|
||||
workpool.insert(id3);
|
||||
|
||||
for (int id2 : edges[id1]) {
|
||||
if (signal_list[id2].in1 == id1)
|
||||
signal_list[id2].in1 = id3;
|
||||
if (signal_list[id2].in2 == id1)
|
||||
signal_list[id2].in2 = id3;
|
||||
if (signal_list[id2].in3 == id1)
|
||||
signal_list[id2].in3 = id3;
|
||||
if (signal_list[id2].in4 == id1)
|
||||
signal_list[id2].in4 = id3;
|
||||
if (run_abc.signal_list[id2].in1 == id1)
|
||||
run_abc.signal_list[id2].in1 = id3;
|
||||
if (run_abc.signal_list[id2].in2 == id1)
|
||||
run_abc.signal_list[id2].in2 = id3;
|
||||
if (run_abc.signal_list[id2].in3 == id1)
|
||||
run_abc.signal_list[id2].in3 = id3;
|
||||
if (run_abc.signal_list[id2].in4 == id1)
|
||||
run_abc.signal_list[id2].in4 = id3;
|
||||
}
|
||||
edges[id1].swap(edges[id3]);
|
||||
|
||||
|
|
@ -724,14 +736,14 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho
|
|||
|
||||
struct abc_output_filter
|
||||
{
|
||||
const AbcModuleState &state;
|
||||
RunAbcState &state;
|
||||
bool got_cr;
|
||||
int escape_seq_state;
|
||||
std::string linebuf;
|
||||
std::string tempdir_name;
|
||||
bool show_tempdir;
|
||||
|
||||
abc_output_filter(const AbcModuleState& state, std::string tempdir_name, bool show_tempdir)
|
||||
abc_output_filter(RunAbcState& state, std::string tempdir_name, bool show_tempdir)
|
||||
: state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir)
|
||||
{
|
||||
got_cr = false;
|
||||
|
|
@ -759,7 +771,7 @@ struct abc_output_filter
|
|||
return;
|
||||
}
|
||||
if (ch == '\n') {
|
||||
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
|
||||
state.logs.log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
|
||||
got_cr = false, linebuf.clear();
|
||||
return;
|
||||
}
|
||||
|
|
@ -772,7 +784,7 @@ struct abc_output_filter
|
|||
{
|
||||
int pi, po;
|
||||
if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
|
||||
log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
|
||||
state.logs.log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
|
||||
pi, state.pi_map.count(pi) ? state.pi_map.at(pi).c_str() : "???",
|
||||
po, state.po_map.count(po) ? state.po_map.at(po).c_str() : "???");
|
||||
return;
|
||||
|
|
@ -858,16 +870,17 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
|
|||
if (dff_mode && clk_sig.empty())
|
||||
log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
|
||||
|
||||
const AbcConfig &config = run_abc.config;
|
||||
if (config.cleanup)
|
||||
tempdir_name = get_base_tmpdir() + "/";
|
||||
run_abc.tempdir_name = get_base_tmpdir() + "/";
|
||||
else
|
||||
tempdir_name = "_tmp_";
|
||||
tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX";
|
||||
tempdir_name = make_temp_dir(tempdir_name);
|
||||
run_abc.tempdir_name = "_tmp_";
|
||||
run_abc.tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX";
|
||||
run_abc.tempdir_name = make_temp_dir(run_abc.tempdir_name);
|
||||
log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
|
||||
module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, config.show_tempdir).c_str());
|
||||
module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str());
|
||||
|
||||
std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name);
|
||||
std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name);
|
||||
|
||||
if (!config.liberty_files.empty() || !config.genlib_files.empty()) {
|
||||
std::string dont_use_args;
|
||||
|
|
@ -933,15 +946,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
|
|||
for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
|
||||
abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3);
|
||||
if (config.abc_dress)
|
||||
abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name);
|
||||
abc_script += stringf("; write_blif %s/output.blif", tempdir_name);
|
||||
abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name);
|
||||
abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name);
|
||||
abc_script = add_echos_to_abc_cmd(abc_script);
|
||||
|
||||
for (size_t i = 0; i+1 < abc_script.size(); i++)
|
||||
if (abc_script[i] == ';' && abc_script[i+1] == ' ')
|
||||
abc_script[i+1] = '\n';
|
||||
|
||||
std::string buffer = stringf("%s/abc.script", tempdir_name);
|
||||
std::string buffer = stringf("%s/abc.script", run_abc.tempdir_name);
|
||||
FILE *f = fopen(buffer.c_str(), "wt");
|
||||
if (f == nullptr)
|
||||
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
|
||||
|
|
@ -997,12 +1010,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
|
|||
handle_loops(assign_map, module);
|
||||
}
|
||||
|
||||
void AbcModuleState::run_abc()
|
||||
void RunAbcState::run()
|
||||
{
|
||||
std::string buffer = stringf("%s/input.blif", tempdir_name);
|
||||
FILE *f = fopen(buffer.c_str(), "wt");
|
||||
if (f == nullptr)
|
||||
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
|
||||
if (f == nullptr) {
|
||||
logs.log("Opening %s for writing failed: %s\n", buffer, strerror(errno));
|
||||
err = true;
|
||||
return;
|
||||
}
|
||||
|
||||
fprintf(f, ".model netlist\n");
|
||||
|
||||
|
|
@ -1117,13 +1133,14 @@ void AbcModuleState::run_abc()
|
|||
fprintf(f, ".end\n");
|
||||
fclose(f);
|
||||
|
||||
log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
|
||||
logs.log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
|
||||
count_gates, GetSize(signal_list), count_input, count_output);
|
||||
if (count_output > 0)
|
||||
{
|
||||
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name);
|
||||
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir));
|
||||
logs.log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir));
|
||||
|
||||
errno = 0;
|
||||
#ifndef YOSYS_LINK_ABC
|
||||
abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
|
||||
int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
|
||||
|
|
@ -1172,10 +1189,10 @@ void AbcModuleState::run_abc()
|
|||
temp_stdouterr_r.close();
|
||||
#endif
|
||||
if (ret != 0) {
|
||||
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
|
||||
logs.log_error("ABC: execution of command \"%s\" failed: return code %d (errno=%d).\n", buffer, ret, errno);
|
||||
return;
|
||||
}
|
||||
did_run_abc = true;
|
||||
did_run = true;
|
||||
return;
|
||||
}
|
||||
log("Don't call ABC as there is nothing to map.\n");
|
||||
|
|
@ -1242,19 +1259,23 @@ void emit_global_input_files(const AbcConfig &config)
|
|||
|
||||
void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module)
|
||||
{
|
||||
if (!did_run_abc) {
|
||||
log_push();
|
||||
log_header(design, "Executed ABC.\n");
|
||||
run_abc.logs.flush();
|
||||
if (!run_abc.did_run) {
|
||||
finish();
|
||||
return;
|
||||
}
|
||||
|
||||
std::string buffer = stringf("%s/%s", tempdir_name, "output.blif");
|
||||
std::string buffer = stringf("%s/%s", run_abc.tempdir_name, "output.blif");
|
||||
std::ifstream ifs;
|
||||
ifs.open(buffer);
|
||||
if (ifs.fail())
|
||||
log_error("Can't open ABC output file `%s'.\n", buffer);
|
||||
|
||||
bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
|
||||
bool builtin_lib = run_abc.config.liberty_files.empty() && run_abc.config.genlib_files.empty();
|
||||
RTLIL::Design *mapped_design = new RTLIL::Design;
|
||||
parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, config.sop_mode);
|
||||
parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, run_abc.config.sop_mode);
|
||||
|
||||
ifs.close();
|
||||
|
||||
|
|
@ -1503,7 +1524,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
|
|||
for (auto &it : cell_stats)
|
||||
log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second);
|
||||
int in_wires = 0, out_wires = 0;
|
||||
for (auto &si : signal_list)
|
||||
for (auto &si : run_abc.signal_list)
|
||||
if (si.is_port) {
|
||||
char buffer[100];
|
||||
snprintf(buffer, 100, "\\ys__n%d", si.id);
|
||||
|
|
@ -1519,20 +1540,22 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
|
|||
}
|
||||
connect(assign_map, module, conn);
|
||||
}
|
||||
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
|
||||
log("ABC RESULTS: internal signals: %8d\n", int(run_abc.signal_list.size()) - in_wires - out_wires);
|
||||
log("ABC RESULTS: input signals: %8d\n", in_wires);
|
||||
log("ABC RESULTS: output signals: %8d\n", out_wires);
|
||||
|
||||
delete mapped_design;
|
||||
finish();
|
||||
}
|
||||
|
||||
void AbcModuleState::finish()
|
||||
{
|
||||
if (config.cleanup)
|
||||
if (run_abc.config.cleanup)
|
||||
{
|
||||
log("Removing temp directory.\n");
|
||||
remove_directory(tempdir_name);
|
||||
remove_directory(run_abc.tempdir_name);
|
||||
}
|
||||
log_pop();
|
||||
}
|
||||
|
||||
// For every signal that connects cells from different sets, or a cell in a set to a cell not in any set,
|
||||
|
|
@ -2182,12 +2205,8 @@ struct AbcPass : public Pass {
|
|||
|
||||
AbcModuleState state(config, initvals);
|
||||
state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str);
|
||||
log_push();
|
||||
log_header(design, "Executing ABC.\n");
|
||||
state.run_abc();
|
||||
state.run_abc.run();
|
||||
state.extract(assign_map, design, mod);
|
||||
state.finish();
|
||||
log_pop();
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -2332,36 +2351,74 @@ struct AbcPass : public Pass {
|
|||
}
|
||||
|
||||
log_header(design, "Summary of detected clock domains:\n");
|
||||
for (auto &it : assigned_cells)
|
||||
log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second),
|
||||
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)),
|
||||
std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)),
|
||||
std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
|
||||
|
||||
{
|
||||
std::vector<std::vector<RTLIL::Cell*>*> cell_sets;
|
||||
for (auto &it : assigned_cells)
|
||||
for (auto &it : assigned_cells) {
|
||||
log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second),
|
||||
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)),
|
||||
std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)),
|
||||
std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
|
||||
cell_sets.push_back(&it.second);
|
||||
}
|
||||
assign_cell_connection_ports(mod, cell_sets, assign_map);
|
||||
}
|
||||
|
||||
// Reserve one core for our main thread, and don't create more worker threads
|
||||
// than ABC runs.
|
||||
int max_threads = assigned_cells.size();
|
||||
if (max_threads <= 1) {
|
||||
// Just do everything on the main thread.
|
||||
max_threads = 0;
|
||||
}
|
||||
#ifdef YOSYS_LINK_ABC
|
||||
// ABC does't support multithreaded calls so don't call it off the main thread.
|
||||
max_threads = 0;
|
||||
#endif
|
||||
int num_worker_threads = ThreadPool::pool_size(1, max_threads);
|
||||
ConcurrentQueue<std::unique_ptr<AbcModuleState>> work_queue(num_worker_threads);
|
||||
ConcurrentQueue<std::unique_ptr<AbcModuleState>> work_finished_queue;
|
||||
int work_finished_count = 0;
|
||||
ThreadPool worker_threads(num_worker_threads, [&](int){
|
||||
while (std::optional<std::unique_ptr<AbcModuleState>> work =
|
||||
work_queue.pop_front()) {
|
||||
// Only the `run_abc` component is safe to touch here!
|
||||
(*work)->run_abc.run();
|
||||
work_finished_queue.push_back(std::move(*work));
|
||||
}
|
||||
});
|
||||
for (auto &it : assigned_cells) {
|
||||
AbcModuleState state(config, initvals);
|
||||
state.clk_polarity = std::get<0>(it.first);
|
||||
state.clk_sig = assign_map(std::get<1>(it.first));
|
||||
state.en_polarity = std::get<2>(it.first);
|
||||
state.en_sig = assign_map(std::get<3>(it.first));
|
||||
state.arst_polarity = std::get<4>(it.first);
|
||||
state.arst_sig = assign_map(std::get<5>(it.first));
|
||||
state.srst_polarity = std::get<6>(it.first);
|
||||
state.srst_sig = assign_map(std::get<7>(it.first));
|
||||
state.prepare_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$");
|
||||
log_push();
|
||||
log_header(design, "Executing ABC.\n");
|
||||
state.run_abc();
|
||||
state.extract(assign_map, design, mod);
|
||||
state.finish();
|
||||
log_pop();
|
||||
// Process ABC results that have already finished before queueing another ABC.
|
||||
// This should keep our memory usage down.
|
||||
while (std::optional<std::unique_ptr<AbcModuleState>> work =
|
||||
work_finished_queue.try_pop_front()) {
|
||||
(*work)->extract(assign_map, design, mod);
|
||||
++work_finished_count;
|
||||
}
|
||||
std::unique_ptr<AbcModuleState> state = std::make_unique<AbcModuleState>(config, initvals);
|
||||
state->clk_polarity = std::get<0>(it.first);
|
||||
state->clk_sig = assign_map(std::get<1>(it.first));
|
||||
state->en_polarity = std::get<2>(it.first);
|
||||
state->en_sig = assign_map(std::get<3>(it.first));
|
||||
state->arst_polarity = std::get<4>(it.first);
|
||||
state->arst_sig = assign_map(std::get<5>(it.first));
|
||||
state->srst_polarity = std::get<6>(it.first);
|
||||
state->srst_sig = assign_map(std::get<7>(it.first));
|
||||
state->prepare_module(design, mod, assign_map, it.second, !state->clk_sig.empty(), "$");
|
||||
if (num_worker_threads > 0) {
|
||||
work_queue.push_back(std::move(state));
|
||||
} else {
|
||||
// Just run everything on the main thread.
|
||||
state->run_abc.run();
|
||||
work_finished_queue.push_back(std::move(state));
|
||||
}
|
||||
}
|
||||
work_queue.close();
|
||||
while (work_finished_count < static_cast<int>(assigned_cells.size())) {
|
||||
std::optional<std::unique_ptr<AbcModuleState>> work =
|
||||
work_finished_queue.pop_front();
|
||||
(*work)->extract(assign_map, design, mod);
|
||||
++work_finished_count;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue