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Run ABCs in parallel.
Large circuits can run hundreds or thousands of ABCs in a single AbcPass. For some circuits, some of those ABC runs can run for hundreds of seconds. Running ABCs in parallel with each other and in parallel with main-thread processing (reading and writing BLIF files, copying ABC BLIF output into the design) can give large speedups.
This commit is contained in:
Robert O'Callahan
Jannis Harder
parent
38f8165c80
commit
27462da208
6 changed files with 362 additions and 88 deletions
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@ -48,6 +48,7 @@
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#include "kernel/ff.h"
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#include "kernel/cost.h"
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#include "kernel/log.h"
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#include "kernel/threading.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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@ -55,6 +56,7 @@
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#include <cerrno>
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#include <sstream>
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#include <climits>
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#include <memory>
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#include <vector>
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#ifndef _WIN32
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@ -153,30 +155,41 @@ struct AbcSigVal {
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using AbcSigMap = SigValMap<AbcSigVal>;
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struct AbcModuleState {
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// Used by off-main-threads. Contains no direct or indirect access to RTLIL.
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struct RunAbcState {
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const AbcConfig &config;
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int map_autoidx = 0;
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std::string tempdir_name;
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std::vector<gate_t> signal_list;
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bool did_run = false;
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bool err = false;
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DeferredLogs logs;
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dict<int, std::string> pi_map, po_map;
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RunAbcState(const AbcConfig &config) : config(config) {}
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void run();
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};
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struct AbcModuleState {
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RunAbcState run_abc;
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int map_autoidx = 0;
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std::vector<RTLIL::SigBit> signal_bits;
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dict<RTLIL::SigBit, int> signal_map;
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FfInitVals &initvals;
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bool had_init = false;
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bool did_run_abc = false;
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bool clk_polarity = false;
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bool en_polarity = false;
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bool arst_polarity = false;
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bool srst_polarity = false;
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RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig;
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dict<int, std::string> pi_map, po_map;
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int undef_bits_lost = 0;
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std::string tempdir_name;
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AbcModuleState(const AbcConfig &config, FfInitVals &initvals)
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: config(config), initvals(initvals) {}
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: run_abc(config), initvals(initvals) {}
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AbcModuleState(AbcModuleState&&) = delete;
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int map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
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void mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig);
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@ -186,7 +199,6 @@ struct AbcModuleState {
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void handle_loops(AbcSigMap &assign_map, RTLIL::Module *module);
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void prepare_module(RTLIL::Design *design, RTLIL::Module *module, AbcSigMap &assign_map, const std::vector<RTLIL::Cell*> &cells,
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bool dff_mode, std::string clk_str);
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void run_abc();
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void extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module);
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void finish();
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};
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@ -200,7 +212,7 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g
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if (signal_map.count(bit) == 0) {
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gate_t gate;
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gate.id = signal_list.size();
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gate.id = run_abc.signal_list.size();
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gate.type = G(NONE);
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gate.in1 = -1;
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gate.in2 = -1;
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@ -212,11 +224,11 @@ int AbcModuleState::map_signal(const AbcSigMap &assign_map, RTLIL::SigBit bit, g
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gate.init = initvals(bit);
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gate.bit_str = std::string(log_signal(bit));
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signal_map[bit] = gate.id;
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signal_list.push_back(std::move(gate));
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run_abc.signal_list.push_back(std::move(gate));
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signal_bits.push_back(bit);
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}
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gate_t &gate = signal_list[signal_map[bit]];
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gate_t &gate = run_abc.signal_list[signal_map[bit]];
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if (gate_type != G(NONE))
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gate.type = gate_type;
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@ -236,7 +248,7 @@ void AbcModuleState::mark_port(const AbcSigMap &assign_map, RTLIL::SigSpec sig)
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{
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for (auto &bit : assign_map(sig))
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if (bit.wire != nullptr && signal_map.count(bit) > 0)
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signal_list[signal_map[bit]].is_port = true;
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run_abc.signal_list[signal_map[bit]].is_port = true;
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}
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bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
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@ -315,7 +327,7 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
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if (keepff) {
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SigBit bit = ff.sig_q;
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if (assign_map(bit).wire != nullptr) {
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signal_list[gate_id].is_port = true;
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run_abc.signal_list[gate_id].is_port = true;
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}
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if (bit.wire != nullptr)
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bit.wire->attributes[ID::keep] = 1;
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@ -467,7 +479,7 @@ std::string AbcModuleState::remap_name(RTLIL::IdString abc_name, RTLIL::Wire **o
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size_t postfix_start = abc_sname.find_first_not_of("0123456789");
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std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
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if (sid < GetSize(signal_list))
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if (sid < GetSize(run_abc.signal_list))
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{
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const auto &bit = signal_bits.at(sid);
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if (bit.wire != nullptr)
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@ -507,7 +519,7 @@ void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edg
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}
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for (auto n : nodes)
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fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, signal_list[n].bit_str.c_str(),
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fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, run_abc.signal_list[n].bit_str.c_str(),
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n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
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for (auto &e : edges)
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@ -529,7 +541,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
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// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
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dict<int, pool<int>> edges;
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std::vector<int> in_edges_count(signal_list.size());
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std::vector<int> in_edges_count(run_abc.signal_list.size());
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pool<int> workpool;
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FILE *dot_f = nullptr;
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@ -538,7 +550,7 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
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// uncomment for troubleshooting the loop detection code
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// dot_f = fopen("test.dot", "w");
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for (auto &g : signal_list) {
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for (auto &g : run_abc.signal_list) {
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if (g.type == G(NONE) || g.type == G(FF) || g.type == G(FF0) || g.type == G(FF1)) {
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workpool.insert(g.id);
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} else {
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@ -621,29 +633,29 @@ void AbcModuleState::handle_loops(AbcSigMap &assign_map, RTLIL::Module *module)
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for (int id2 : edges[id1]) {
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if (first_line)
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log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
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signal_list[id1].bit_str, signal_list[id2].bit_str);
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run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str);
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else
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log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
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signal_list[id1].bit_str, signal_list[id2].bit_str);
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run_abc.signal_list[id1].bit_str, run_abc.signal_list[id2].bit_str);
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first_line = false;
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}
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int id3 = map_signal(assign_map, RTLIL::SigSpec(wire));
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signal_list[id1].is_port = true;
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signal_list[id3].is_port = true;
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run_abc.signal_list[id1].is_port = true;
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run_abc.signal_list[id3].is_port = true;
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log_assert(id3 == int(in_edges_count.size()));
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in_edges_count.push_back(0);
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workpool.insert(id3);
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for (int id2 : edges[id1]) {
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if (signal_list[id2].in1 == id1)
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signal_list[id2].in1 = id3;
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if (signal_list[id2].in2 == id1)
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signal_list[id2].in2 = id3;
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if (signal_list[id2].in3 == id1)
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signal_list[id2].in3 = id3;
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if (signal_list[id2].in4 == id1)
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signal_list[id2].in4 = id3;
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if (run_abc.signal_list[id2].in1 == id1)
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run_abc.signal_list[id2].in1 = id3;
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if (run_abc.signal_list[id2].in2 == id1)
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run_abc.signal_list[id2].in2 = id3;
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if (run_abc.signal_list[id2].in3 == id1)
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run_abc.signal_list[id2].in3 = id3;
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if (run_abc.signal_list[id2].in4 == id1)
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run_abc.signal_list[id2].in4 = id3;
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}
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edges[id1].swap(edges[id3]);
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@ -724,14 +736,14 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho
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struct abc_output_filter
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{
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const AbcModuleState &state;
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RunAbcState &state;
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bool got_cr;
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int escape_seq_state;
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std::string linebuf;
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std::string tempdir_name;
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bool show_tempdir;
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abc_output_filter(const AbcModuleState& state, std::string tempdir_name, bool show_tempdir)
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abc_output_filter(RunAbcState& state, std::string tempdir_name, bool show_tempdir)
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: state(state), tempdir_name(tempdir_name), show_tempdir(show_tempdir)
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{
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got_cr = false;
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@ -759,7 +771,7 @@ struct abc_output_filter
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return;
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}
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if (ch == '\n') {
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log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
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state.logs.log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
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got_cr = false, linebuf.clear();
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return;
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}
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@ -772,7 +784,7 @@ struct abc_output_filter
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{
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int pi, po;
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if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
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log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
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state.logs.log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
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pi, state.pi_map.count(pi) ? state.pi_map.at(pi).c_str() : "???",
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po, state.po_map.count(po) ? state.po_map.at(po).c_str() : "???");
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return;
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@ -858,16 +870,17 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
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if (dff_mode && clk_sig.empty())
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log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
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const AbcConfig &config = run_abc.config;
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if (config.cleanup)
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tempdir_name = get_base_tmpdir() + "/";
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run_abc.tempdir_name = get_base_tmpdir() + "/";
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else
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tempdir_name = "_tmp_";
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tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX";
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tempdir_name = make_temp_dir(tempdir_name);
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run_abc.tempdir_name = "_tmp_";
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run_abc.tempdir_name += proc_program_prefix() + "yosys-abc-XXXXXX";
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run_abc.tempdir_name = make_temp_dir(run_abc.tempdir_name);
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log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
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module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, config.show_tempdir).c_str());
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module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str());
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std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name);
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std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", run_abc.tempdir_name);
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if (!config.liberty_files.empty() || !config.genlib_files.empty()) {
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std::string dont_use_args;
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@ -933,15 +946,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
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for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
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abc_script = abc_script.substr(0, pos) + config.lutin_shared + abc_script.substr(pos+3);
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if (config.abc_dress)
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abc_script += stringf("; dress \"%s/input.blif\"", tempdir_name);
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abc_script += stringf("; write_blif %s/output.blif", tempdir_name);
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abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name);
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abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name);
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abc_script = add_echos_to_abc_cmd(abc_script);
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for (size_t i = 0; i+1 < abc_script.size(); i++)
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if (abc_script[i] == ';' && abc_script[i+1] == ' ')
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abc_script[i+1] = '\n';
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std::string buffer = stringf("%s/abc.script", tempdir_name);
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std::string buffer = stringf("%s/abc.script", run_abc.tempdir_name);
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FILE *f = fopen(buffer.c_str(), "wt");
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if (f == nullptr)
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log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
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@ -997,12 +1010,15 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
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handle_loops(assign_map, module);
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}
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void AbcModuleState::run_abc()
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void RunAbcState::run()
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{
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std::string buffer = stringf("%s/input.blif", tempdir_name);
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FILE *f = fopen(buffer.c_str(), "wt");
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if (f == nullptr)
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log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
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if (f == nullptr) {
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logs.log("Opening %s for writing failed: %s\n", buffer, strerror(errno));
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err = true;
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return;
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}
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fprintf(f, ".model netlist\n");
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@ -1117,13 +1133,14 @@ void AbcModuleState::run_abc()
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fprintf(f, ".end\n");
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fclose(f);
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log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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logs.log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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count_gates, GetSize(signal_list), count_input, count_output);
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if (count_output > 0)
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{
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buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name);
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log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir));
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logs.log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir));
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errno = 0;
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#ifndef YOSYS_LINK_ABC
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abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
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int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
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@ -1172,10 +1189,10 @@ void AbcModuleState::run_abc()
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temp_stdouterr_r.close();
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#endif
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if (ret != 0) {
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log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
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logs.log_error("ABC: execution of command \"%s\" failed: return code %d (errno=%d).\n", buffer, ret, errno);
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return;
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}
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did_run_abc = true;
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did_run = true;
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return;
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}
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log("Don't call ABC as there is nothing to map.\n");
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@ -1242,19 +1259,23 @@ void emit_global_input_files(const AbcConfig &config)
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void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL::Module *module)
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{
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if (!did_run_abc) {
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log_push();
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log_header(design, "Executed ABC.\n");
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run_abc.logs.flush();
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if (!run_abc.did_run) {
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finish();
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return;
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}
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std::string buffer = stringf("%s/%s", tempdir_name, "output.blif");
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std::string buffer = stringf("%s/%s", run_abc.tempdir_name, "output.blif");
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std::ifstream ifs;
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ifs.open(buffer);
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if (ifs.fail())
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log_error("Can't open ABC output file `%s'.\n", buffer);
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bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
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bool builtin_lib = run_abc.config.liberty_files.empty() && run_abc.config.genlib_files.empty();
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RTLIL::Design *mapped_design = new RTLIL::Design;
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parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, config.sop_mode);
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parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, run_abc.config.sop_mode);
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ifs.close();
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@ -1503,7 +1524,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
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for (auto &it : cell_stats)
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log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second);
|
||||
int in_wires = 0, out_wires = 0;
|
||||
for (auto &si : signal_list)
|
||||
for (auto &si : run_abc.signal_list)
|
||||
if (si.is_port) {
|
||||
char buffer[100];
|
||||
snprintf(buffer, 100, "\\ys__n%d", si.id);
|
||||
|
|
@ -1519,20 +1540,22 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
|
|||
}
|
||||
connect(assign_map, module, conn);
|
||||
}
|
||||
log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
|
||||
log("ABC RESULTS: internal signals: %8d\n", int(run_abc.signal_list.size()) - in_wires - out_wires);
|
||||
log("ABC RESULTS: input signals: %8d\n", in_wires);
|
||||
log("ABC RESULTS: output signals: %8d\n", out_wires);
|
||||
|
||||
delete mapped_design;
|
||||
finish();
|
||||
}
|
||||
|
||||
void AbcModuleState::finish()
|
||||
{
|
||||
if (config.cleanup)
|
||||
if (run_abc.config.cleanup)
|
||||
{
|
||||
log("Removing temp directory.\n");
|
||||
remove_directory(tempdir_name);
|
||||
remove_directory(run_abc.tempdir_name);
|
||||
}
|
||||
log_pop();
|
||||
}
|
||||
|
||||
// For every signal that connects cells from different sets, or a cell in a set to a cell not in any set,
|
||||
|
|
@ -2182,12 +2205,8 @@ struct AbcPass : public Pass {
|
|||
|
||||
AbcModuleState state(config, initvals);
|
||||
state.prepare_module(design, mod, assign_map, cells, dff_mode, clk_str);
|
||||
log_push();
|
||||
log_header(design, "Executing ABC.\n");
|
||||
state.run_abc();
|
||||
state.run_abc.run();
|
||||
state.extract(assign_map, design, mod);
|
||||
state.finish();
|
||||
log_pop();
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -2332,36 +2351,74 @@ struct AbcPass : public Pass {
|
|||
}
|
||||
|
||||
log_header(design, "Summary of detected clock domains:\n");
|
||||
for (auto &it : assigned_cells)
|
||||
log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second),
|
||||
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)),
|
||||
std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)),
|
||||
std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
|
||||
|
||||
{
|
||||
std::vector<std::vector<RTLIL::Cell*>*> cell_sets;
|
||||
for (auto &it : assigned_cells)
|
||||
for (auto &it : assigned_cells) {
|
||||
log(" %d cells in clk=%s%s, en=%s%s, arst=%s%s, srst=%s%s\n", GetSize(it.second),
|
||||
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
|
||||
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)),
|
||||
std::get<4>(it.first) ? "" : "!", log_signal(std::get<5>(it.first)),
|
||||
std::get<6>(it.first) ? "" : "!", log_signal(std::get<7>(it.first)));
|
||||
cell_sets.push_back(&it.second);
|
||||
}
|
||||
assign_cell_connection_ports(mod, cell_sets, assign_map);
|
||||
}
|
||||
|
||||
// Reserve one core for our main thread, and don't create more worker threads
|
||||
// than ABC runs.
|
||||
int max_threads = assigned_cells.size();
|
||||
if (max_threads <= 1) {
|
||||
// Just do everything on the main thread.
|
||||
max_threads = 0;
|
||||
}
|
||||
#ifdef YOSYS_LINK_ABC
|
||||
// ABC does't support multithreaded calls so don't call it off the main thread.
|
||||
max_threads = 0;
|
||||
#endif
|
||||
int num_worker_threads = ThreadPool::pool_size(1, max_threads);
|
||||
ConcurrentQueue<std::unique_ptr<AbcModuleState>> work_queue(num_worker_threads);
|
||||
ConcurrentQueue<std::unique_ptr<AbcModuleState>> work_finished_queue;
|
||||
int work_finished_count = 0;
|
||||
ThreadPool worker_threads(num_worker_threads, [&](int){
|
||||
while (std::optional<std::unique_ptr<AbcModuleState>> work =
|
||||
work_queue.pop_front()) {
|
||||
// Only the `run_abc` component is safe to touch here!
|
||||
(*work)->run_abc.run();
|
||||
work_finished_queue.push_back(std::move(*work));
|
||||
}
|
||||
});
|
||||
for (auto &it : assigned_cells) {
|
||||
AbcModuleState state(config, initvals);
|
||||
state.clk_polarity = std::get<0>(it.first);
|
||||
state.clk_sig = assign_map(std::get<1>(it.first));
|
||||
state.en_polarity = std::get<2>(it.first);
|
||||
state.en_sig = assign_map(std::get<3>(it.first));
|
||||
state.arst_polarity = std::get<4>(it.first);
|
||||
state.arst_sig = assign_map(std::get<5>(it.first));
|
||||
state.srst_polarity = std::get<6>(it.first);
|
||||
state.srst_sig = assign_map(std::get<7>(it.first));
|
||||
state.prepare_module(design, mod, assign_map, it.second, !state.clk_sig.empty(), "$");
|
||||
log_push();
|
||||
log_header(design, "Executing ABC.\n");
|
||||
state.run_abc();
|
||||
state.extract(assign_map, design, mod);
|
||||
state.finish();
|
||||
log_pop();
|
||||
// Process ABC results that have already finished before queueing another ABC.
|
||||
// This should keep our memory usage down.
|
||||
while (std::optional<std::unique_ptr<AbcModuleState>> work =
|
||||
work_finished_queue.try_pop_front()) {
|
||||
(*work)->extract(assign_map, design, mod);
|
||||
++work_finished_count;
|
||||
}
|
||||
std::unique_ptr<AbcModuleState> state = std::make_unique<AbcModuleState>(config, initvals);
|
||||
state->clk_polarity = std::get<0>(it.first);
|
||||
state->clk_sig = assign_map(std::get<1>(it.first));
|
||||
state->en_polarity = std::get<2>(it.first);
|
||||
state->en_sig = assign_map(std::get<3>(it.first));
|
||||
state->arst_polarity = std::get<4>(it.first);
|
||||
state->arst_sig = assign_map(std::get<5>(it.first));
|
||||
state->srst_polarity = std::get<6>(it.first);
|
||||
state->srst_sig = assign_map(std::get<7>(it.first));
|
||||
state->prepare_module(design, mod, assign_map, it.second, !state->clk_sig.empty(), "$");
|
||||
if (num_worker_threads > 0) {
|
||||
work_queue.push_back(std::move(state));
|
||||
} else {
|
||||
// Just run everything on the main thread.
|
||||
state->run_abc.run();
|
||||
work_finished_queue.push_back(std::move(state));
|
||||
}
|
||||
}
|
||||
work_queue.close();
|
||||
while (work_finished_count < static_cast<int>(assigned_cells.size())) {
|
||||
std::optional<std::unique_ptr<AbcModuleState>> work =
|
||||
work_finished_queue.pop_front();
|
||||
(*work)->extract(assign_map, design, mod);
|
||||
++work_finished_count;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue