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Add new tests for Anlogic architecture

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Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
This commit is contained in:
SergeyDegtyar 2019-09-23 12:12:02 +03:00
parent 7e8f7f4c59
commit 27377c4663
23 changed files with 536 additions and 0 deletions
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tests/anlogic/add_sub.ys Normal file
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read_verilog add_sub.v
hierarchy -top top
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:AL_MAP_ADDER
select -assert-count 4 t:AL_MAP_LUT1
select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D