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verilog: strip leading and trailing spaces in macro args

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This commit is contained in:
Zachary Snow 2021-01-28 11:26:21 -05:00
parent 98afe2b758
commit 27257a419f
2 changed files with 25 additions and 1 deletions
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6
frontends/verilog/preproc.cc
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@ -390,12 +390,16 @@ static void input_file(std::istream &f, std::string filename)
// the argument list); false if we finished with ','.
static bool read_argument(std::string &dest)
{
skip_spaces();
std::vector<char> openers;
for (;;) {
std::string tok = next_token(true);
if (tok == ")") {
if (openers.empty())
if (openers.empty()) {
while (dest.size() && (dest.back() == ' ' || dest.back() == '\t'))
dest = dest.substr(0, dest.size() - 1);
return true;
}
if (openers.back() != '(')
log_error("Mismatched brackets in macro argument: %c and %c.\n",
openers.back(), tok[0]);

20
tests/simple/macro_arg_surrounding_spaces.v Normal file
View file

@ -0,0 +1,20 @@
module top(
IDENT_V_,
IDENT_W_,
IDENT_X_,
IDENT_Y_,
IDENT_Z_,
IDENT_A_,
IDENT_B_,
IDENT_C_
);
`define MACRO(dummy, x) IDENT_``x``_
output wire IDENT_V_;
output wire `MACRO(_,W);
output wire `MACRO(_, X);
output wire `MACRO(_,Y );
output wire `MACRO(_, Z );
output wire `MACRO(_, A);
output wire `MACRO(_,B );
output wire `MACRO(_, C );
endmodule