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Added test cases

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This commit is contained in:
Miodrag Milanovic 2022-02-15 09:35:53 +01:00
parent fb22d7cdc4
commit 271ac28b41
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70
tests/sim/tb/tb_adlatch.v Executable file
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`timescale 1ns/1ns
module tb_adlatch();
reg clk = 0;
reg rst = 0;
reg en = 0;
reg d = 0;
wire q;
adlatch uut(.d(d),.rst(rst),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_adlatch");
$dumpvars(0,tb_adlatch);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule