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Added test cases

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This commit is contained in:
Miodrag Milanovic 2022-02-15 09:35:53 +01:00
parent fb22d7cdc4
commit 271ac28b41
39 changed files with 897 additions and 0 deletions
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40
tests/sim/tb/tb_adff.v Executable file
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`timescale 1ns/1ns
module tb_adff();
reg clk = 0;
reg rst = 0;
reg d = 0;
wire q;
adff uut(.clk(clk),.d(d),.rst(rst),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_adff");
$dumpvars(0,tb_adff);
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

58
tests/sim/tb/tb_adffe.v Executable file
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`timescale 1ns/1ns
module tb_adffe();
reg clk = 0;
reg rst = 0;
reg d = 0;
reg en = 0;
wire q;
adffe uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_adffe");
$dumpvars(0,tb_adffe);
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

70
tests/sim/tb/tb_adlatch.v Executable file
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`timescale 1ns/1ns
module tb_adlatch();
reg clk = 0;
reg rst = 0;
reg en = 0;
reg d = 0;
wire q;
adlatch uut(.d(d),.rst(rst),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_adlatch");
$dumpvars(0,tb_adlatch);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

73
tests/sim/tb/tb_aldff.v Executable file
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`timescale 1ns/1ns
module tb_aldff();
reg clk = 0;
reg aload = 0;
reg [0:3] d = 4'b0000;
reg [0:3] ad = 4'b1010;
wire [0:3] q;
aldff uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_aldff");
$dumpvars(0,tb_aldff);
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 1;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 0;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 1;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 0;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
$finish;
end
endmodule

75
tests/sim/tb/tb_aldffe.v Executable file
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`timescale 1ns/1ns
module tb_aldffe();
reg clk = 0;
reg aload = 0;
reg [0:3] d = 4'b0000;
reg [0:3] ad = 4'b1010;
reg en = 0;
wire [0:3] q;
aldffe uut(.clk(clk),.d(d),.ad(ad),.aload(aload),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_aldffe");
$dumpvars(0,tb_aldffe);
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 1;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 0;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
en = 1;
aload = 1;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
aload = 0;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
d = 4'b1100;
#10
d = 4'b0011;
#10
$finish;
end
endmodule

47
tests/sim/tb/tb_dff.v Executable file
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`timescale 1ns/1ns
module tb_dff();
reg clk = 0;
reg d = 0;
wire q;
dff uut(.clk(clk),.d(d),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_dff");
$dumpvars(0,tb_dff);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

42
tests/sim/tb/tb_dffe.v Executable file
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`timescale 1ns/1ns
module tb_dffe();
reg clk = 0;
reg en = 0;
reg d = 0;
wire q;
dffe uut(.clk(clk),.d(d),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_dffe");
$dumpvars(0,tb_dffe);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

69
tests/sim/tb/tb_dffsr.v Executable file
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`timescale 1ns/1ns
module tb_dffsr();
reg clk = 0;
reg d = 0;
reg set = 0;
reg clr = 0;
wire q;
dffsr uut(.d(d),.clk(clk),.set(set),.clr(clr),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_dffsr");
$dumpvars(0,tb_dffsr);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
clr = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
clr = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
set = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
set = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

50
tests/sim/tb/tb_dlatch.v Executable file
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`timescale 1ns/1ns
module tb_dlatch();
reg clk = 0;
reg en = 0;
reg d = 0;
wire q;
dlatch uut(.d(d),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_dlatch");
$dumpvars(0,tb_dlatch);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

48
tests/sim/tb/tb_sdff.v Executable file
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`timescale 1ns/1ns
module tb_sdff();
reg clk = 0;
reg rst = 0;
reg d = 0;
wire q;
sdff uut(.clk(clk),.d(d),.rst(rst),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_sdff");
$dumpvars(0,tb_sdff);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

79
tests/sim/tb/tb_sdffce.v Executable file
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`timescale 1ns/1ns
module tb_sdffce();
reg clk = 0;
reg rst = 0;
reg d = 0;
reg en = 0;
wire q;
sdffce uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_sdffce");
$dumpvars(0,tb_sdffce);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule

70
tests/sim/tb/tb_sdffe.v Executable file
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`timescale 1ns/1ns
module tb_sdffe();
reg clk = 0;
reg rst = 0;
reg d = 0;
reg en = 0;
wire q;
sdffe uut(.clk(clk),.d(d),.rst(rst),.en(en),.q(q));
always
#(5) clk <= !clk;
initial
begin
$dumpfile("tb_sdffe");
$dumpvars(0,tb_sdffe);
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
en = 1;
rst = 1;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
rst = 0;
#10
d = 1;
#10
d = 0;
#10
d = 1;
#10
d = 0;
#10
$finish;
end
endmodule