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Added test cases

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This commit is contained in:
Miodrag Milanovic 2022-02-15 09:35:53 +01:00
parent fb22d7cdc4
commit 271ac28b41
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tests/sim/sim_adffe.ys Normal file
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read_verilog adffe.v
proc
opt_dff
stat
select -assert-count 1 t:$adffe
sim -clock clk -r tb_adffe.fst -scope tb_adffe.uut -sim-cmp adffe