mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00
Code Activity

Added test cases

Browse source
This commit is contained in:
Miodrag Milanovic 2022-02-15 09:35:53 +01:00
parent fb22d7cdc4
commit 271ac28b41
39 changed files with 897 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/sim/dlatch.v Normal file
View file

@ -0,0 +1,6 @@
module dlatch( input d, en, output reg q );
always @* begin
if ( en )
q = d;
end
endmodule