mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-24 08:24:35 +00:00
Code Activity

Added test cases

Browse source
This commit is contained in:
Miodrag Milanovic 2022-02-15 09:35:53 +01:00
parent fb22d7cdc4
commit 271ac28b41
39 changed files with 897 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

9
tests/sim/dffsr.v Normal file
View file

@ -0,0 +1,9 @@
module dffsr( input clk, d, clr, set, output reg q );
always @( posedge clk, posedge set, posedge clr)
if ( clr )
q <= 0;
else if (set)
q <= 1;
else
q <= d;
endmodule