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Added test cases

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This commit is contained in:
Miodrag Milanovic 2022-02-15 09:35:53 +01:00
parent fb22d7cdc4
commit 271ac28b41
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8
tests/sim/adlatch.v Normal file
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module adlatch( input d, rst, en, output reg q );
always @* begin
if (rst)
q = 0;
else if (en)
q = d;
end
endmodule