mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-03 21:01:23 +00:00
Code Activity

Revert "Add a xilinx_finalise pass"

Browse source 
This reverts commit 23d90e0439.
This commit is contained in:
Eddie Hung 2019-09-23 19:52:55 -07:00
parent 0f53893104
commit 27167848f4
3 changed files with 0 additions and 87 deletions
Download patch file Download diff file Expand all files Collapse all files

1
techlibs/xilinx/Makefile.inc
View file

@ -1,6 +1,5 @@
OBJS += techlibs/xilinx/synth_xilinx.o OBJS += techlibs/xilinx/synth_xilinx.o
OBJS += techlibs/xilinx/xilinx_finalise.o
GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_36.vh
GENFILES += techlibs/xilinx/brams_init_32.vh GENFILES += techlibs/xilinx/brams_init_32.vh

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -512,8 +512,6 @@ struct SynthXilinxPass : public ScriptPass
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')"); run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
if (help_mode || ise) if (help_mode || ise)
run("extractinv -inv INV O:I", "(only if '-ise')"); run("extractinv -inv INV O:I", "(only if '-ise')");
if (help_mode || !nodsp)
run("xilinx_finalise", "(skip if '-nodsp')");
} }
if (check_label("check")) { if (check_label("check")) {

84
techlibs/xilinx/xilinx_finalise.cc
View file

@ -1,84 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* (C) 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct XilinxFinalisePass : public Pass
{
XilinxFinalisePass() : Pass("xilinx_finalise", "") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" xilinx_finalise [options]\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
break;
}
extra_args(args, argidx, design);
log_header(design, "Executing XILINX_FINALISE pass.\n");
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) {
if (cell->type != ID(DSP48E1))
continue;
for (auto &conn : cell->connections_) {
if (!cell->output(conn.first))
continue;
bool purge = true;
for (auto &chunk : conn.second.chunks()) {
auto it = chunk.wire->attributes.find(ID(unused_bits));
if (it == chunk.wire->attributes.end())
continue;
std::string unused_bits = stringf("%d", chunk.offset);
for (auto i = 1; i < chunk.width; i++)
unused_bits += stringf(" %d", i+chunk.offset);
if (it->second.decode_string().find(unused_bits) == std::string::npos) {
purge = false;
break;
}
}
if (purge) {
log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second));
conn.second = SigSpec();
}
}
}
}
} XilinxFinalisePass;
PRIVATE_NAMESPACE_END