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Merge a8ff020829 into 47ca09a016

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Robert O'Callahan 2025-10-08 13:37:04 +13:00 • committed by GitHub
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21 changed files with 75 additions and 78 deletions
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2
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -3433,7 +3433,7 @@ struct CxxrtlWorker {
if (!design->selected_whole_module(module)) if (!design->selected_whole_module(module))
if (design->selected_module(module)) if (design->selected_module(module))
log_cmd_error("Can't handle partially selected module `%s'!\n", id2cstr(module->name)); log_cmd_error("Can't handle partially selected module `%s'!\n", log_id(module->name));
if (!design->selected_module(module)) if (!design->selected_module(module))
continue; continue;

14
docs/source/code_examples/functional/dummy.cc
View file

@ -24,19 +24,19 @@ struct FunctionalDummyBackend : public Backend {
// write node functions // write node functions
for (auto node : ir) for (auto node : ir)
*f << " assign " << id2cstr(node.name()) *f << " assign " << log_id(node.name())
<< " = " << node.to_string() << "\n"; << " = " << node.to_string() << "\n";
*f << "\n"; *f << "\n";
// write outputs and next state // write outputs and next state
for (auto output : ir.outputs()) for (auto output : ir.outputs())
*f << " " << id2cstr(output->kind) *f << " " << log_id(output->kind)
<< " " << id2cstr(output->name) << " " << log_id(output->name)
<< " = " << id2cstr(output->value().name()) << "\n"; << " = " << log_id(output->value().name()) << "\n";
for (auto state : ir.states()) for (auto state : ir.states())
*f << " " << id2cstr(state->kind) *f << " " << log_id(state->kind)
<< " " << id2cstr(state->name) << " " << log_id(state->name)
<< " = " << id2cstr(state->next_value().name()) << "\n"; << " = " << log_id(state->next_value().name()) << "\n";
} }
} }
} FunctionalDummyBackend; } FunctionalDummyBackend;

6
docs/source/code_examples/stubnets/stubnets.cc
View file

@ -27,7 +27,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// count output lines for this module (needed only for summary output at the end) // count output lines for this module (needed only for summary output at the end)
int line_count = 0; int line_count = 0;
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name)); log("Looking for stub wires in module %s:\n", log_id(module->name));
// For all ports on all cells // For all ports on all cells
for (auto &cell_iter : module->cells_) for (auto &cell_iter : module->cells_)
@ -74,11 +74,11 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// report stub bits and/or stub wires, don't report single bits // report stub bits and/or stub wires, don't report single bits
// if called with report_bits set to false. // if called with report_bits set to false.
if (GetSize(stub_bits) == GetSize(sig)) { if (GetSize(stub_bits) == GetSize(sig)) {
log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name)); log(" found stub wire: %s\n", log_id(wire->name));
} else { } else {
if (!report_bits) if (!report_bits)
continue; continue;
log(" found wire with stub bits: %s [", RTLIL::id2cstr(wire->name)); log(" found wire with stub bits: %s [", log_id(wire->name));
for (int bit : stub_bits) for (int bit : stub_bits)
log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit); log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
log("]\n"); log("]\n");

2
docs/source/yosys_internals/extending_yosys/extensions.rst
View file

@ -231,7 +231,7 @@ Use ``log_error()`` to report a non-recoverable error:
if (design->modules.count(module->name) != 0) if (design->modules.count(module->name) != 0)
log_error("A module with the name %s already exists!\n", log_error("A module with the name %s already exists!\n",
RTLIL::id2cstr(module->name)); log_id(module->name));
Use ``log_cmd_error()`` to report a recoverable error: Use ``log_cmd_error()`` to report a recoverable error:

2
docs/source/yosys_internals/extending_yosys/functional_ir.rst
View file

@ -181,7 +181,7 @@ pointer ``f`` to the output file, or stdout if none is given.
For this minimal example all we are doing is printing out each node. The For this minimal example all we are doing is printing out each node. The
``node.name()`` method returns an ``RTLIL::IdString``, which we convert for ``node.name()`` method returns an ``RTLIL::IdString``, which we convert for
printing with ``id2cstr()``. Then, to print the function of the node, we use printing with ``log_id()``. Then, to print the function of the node, we use
``node.to_string()`` which gives us a string of the form ``function(args)``. The ``node.to_string()`` which gives us a string of the form ``function(args)``. The
``function`` part is the result of ``Functional::IR::fn_to_string(node.fn())``; ``function`` part is the result of ``Functional::IR::fn_to_string(node.fn())``;
while ``args`` is the zero or more arguments passed to the function, most while ``args`` is the zero or more arguments passed to the function, most

4
frontends/verific/verific.cc
View file

@ -1492,10 +1492,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
design->add(module); design->add(module);
if (is_blackbox(nl)) { if (is_blackbox(nl)) {
log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); log("Importing blackbox module %s.\n", log_id(module->name));
module->set_bool_attribute(ID::blackbox); module->set_bool_attribute(ID::blackbox);
} else { } else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", log_id(module->name));
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl);
if (module->name.isPublic()) if (module->name.isPublic())

6
kernel/rtlil.cc
View file

@ -1488,7 +1488,7 @@ void RTLIL::Module::makeblackbox()
void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &) void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &)
{ {
log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name)); log_error("Class doesn't support expand_interfaces (module: `%s')!\n", log_id(name));
} }
bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *) bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *)
@ -1500,7 +1500,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString
{ {
if (mayfail) if (mayfail)
return RTLIL::IdString(); return RTLIL::IdString();
log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); log_error("Module `%s' is used with parameters but is not parametric!\n", log_id(name));
} }
@ -1508,7 +1508,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString
{ {
if (mayfail) if (mayfail)
return RTLIL::IdString(); return RTLIL::IdString();
log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); log_error("Module `%s' is used with parameters but is not parametric!\n", log_id(name));
} }
size_t RTLIL::Module::count_id(const RTLIL::IdString& id) size_t RTLIL::Module::count_id(const RTLIL::IdString& id)

1
kernel/rtlil.h
View file

@ -593,6 +593,7 @@ namespace RTLIL {
return unescape_id(str.str()); return unescape_id(str.str());
} }
[[deprecated("Use log_id() instead")]]
static inline const char *id2cstr(const RTLIL::IdString &str) { static inline const char *id2cstr(const RTLIL::IdString &str) {
return log_id(str); return log_id(str);
} }

6
passes/cmds/scc.cc
View file

@ -87,7 +87,7 @@ struct SccWorker
RTLIL::Cell *c = cellStack.back(); RTLIL::Cell *c = cellStack.back();
cellStack.pop_back(); cellStack.pop_back();
cellsOnStack.erase(c); cellsOnStack.erase(c);
log(" %s", RTLIL::id2cstr(c->name)); log(" %s", log_id(c->name));
cell2scc[c] = sccList.size(); cell2scc[c] = sccList.size();
scc.insert(c); scc.insert(c);
} }
@ -201,7 +201,7 @@ struct SccWorker
if (!nofeedbackMode && cellToNextCell[cell].count(cell)) { if (!nofeedbackMode && cellToNextCell[cell].count(cell)) {
log("Found an SCC:"); log("Found an SCC:");
pool<RTLIL::Cell*> scc; pool<RTLIL::Cell*> scc;
log(" %s", RTLIL::id2cstr(cell->name)); log(" %s", log_id(cell->name));
cell2scc[cell] = sccList.size(); cell2scc[cell] = sccList.size();
scc.insert(cell); scc.insert(cell);
sccList.push_back(scc); sccList.push_back(scc);
@ -221,7 +221,7 @@ struct SccWorker
run(cell, 0, maxDepth); run(cell, 0, maxDepth);
} }
log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name)); log("Found %d SCCs in module %s.\n", int(sccList.size()), log_id(module->name));
} }
void select(RTLIL::Selection &sel) void select(RTLIL::Selection &sel)

18
passes/cmds/select.cc
View file

@ -25,8 +25,6 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
static std::vector<RTLIL::Selection> work_stack; static std::vector<RTLIL::Selection> work_stack;
static bool match_ids(RTLIL::IdString id, const std::string &pattern) static bool match_ids(RTLIL::IdString id, const std::string &pattern)
@ -1022,9 +1020,9 @@ static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::S
for (auto mod : design->all_selected_modules()) for (auto mod : design->all_selected_modules())
{ {
if (whole_modules && sel->selected_whole_module(mod->name)) if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name)); desc += stringf("%s\n", log_id(mod->name));
for (auto it : mod->selected_members()) for (auto it : mod->selected_members())
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name)); desc += stringf("%s/%s\n", log_id(mod->name), log_id(it->name));
} }
if (push_selection) design->pop_selection(); if (push_selection) design->pop_selection();
return desc; return desc;
@ -1414,7 +1412,7 @@ struct SelectPass : public Pass {
if (arg == "-module" && argidx+1 < args.size()) { if (arg == "-module" && argidx+1 < args.size()) {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->module(mod_name) == nullptr) if (design->module(mod_name) == nullptr)
log_cmd_error("No such module: %s\n", id2cstr(mod_name)); log_cmd_error("No such module: %s\n", log_id(mod_name));
design->selected_active_module = mod_name.str(); design->selected_active_module = mod_name.str();
got_module = true; got_module = true;
continue; continue;
@ -1527,10 +1525,10 @@ struct SelectPass : public Pass {
for (auto mod : design->all_selected_modules()) for (auto mod : design->all_selected_modules())
{ {
if (sel->selected_whole_module(mod->name) && list_mode) if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name)); log("%s\n", log_id(mod->name));
if (!list_mod_mode) if (!list_mod_mode)
for (auto it : mod->selected_members()) for (auto it : mod->selected_members())
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name)) LOG_OBJECT("%s/%s\n", log_id(mod->name), log_id(it->name))
} }
if (count_mode) if (count_mode)
{ {
@ -1654,10 +1652,10 @@ struct SelectPass : public Pass {
if (sel.full_selection) if (sel.full_selection)
log("*\n"); log("*\n");
for (auto &it : sel.selected_modules) for (auto &it : sel.selected_modules)
log("%s\n", id2cstr(it)); log("%s\n", log_id(it));
for (auto &it : sel.selected_members) for (auto &it : sel.selected_members)
for (auto &it2 : it.second) for (auto &it2 : it.second)
log("%s/%s\n", id2cstr(it.first), id2cstr(it2)); log("%s/%s\n", log_id(it.first), log_id(it2));
return; return;
} }
@ -1779,7 +1777,7 @@ static void log_matches(const char *title, Module *module, const T &list)
log("\n%d %s:\n", int(matches.size()), title); log("\n%d %s:\n", int(matches.size()), title);
std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str()); std::sort(matches.begin(), matches.end(), RTLIL::sort_by_id_str());
for (auto id : matches) for (auto id : matches)
log(" %s\n", RTLIL::id2cstr(id)); log(" %s\n", log_id(id));
} }
} }

4
passes/cmds/test_select.cc
View file

@ -144,10 +144,10 @@ struct TestSelectPass : public Pass {
for (auto *mod : sub_sel) { for (auto *mod : sub_sel) {
if (mod->is_selected_whole()) { if (mod->is_selected_whole()) {
log_debug(" Adding %s.\n", id2cstr(mod->name)); log_debug(" Adding %s.\n", log_id(mod->name));
selected_modules.insert(mod->name); selected_modules.insert(mod->name);
} else for (auto *memb : mod->selected_members()) { } else for (auto *memb : mod->selected_members()) {
log_debug(" Adding %s.%s.\n", id2cstr(mod->name), id2cstr(memb->name)); log_debug(" Adding %s.%s.\n", log_id(mod->name), log_id(memb->name));
selected_members[mod->name].insert(memb); selected_members[mod->name].insert(memb);
} }
} }

4
passes/equiv/equiv_make.cc
View file

@ -284,11 +284,11 @@ struct EquivMakeWorker
for (int i = 0; i < wire->width; i++) { for (int i = 0; i < wire->width; i++) {
if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); log(" Skipping signal bit %s [%d]: undriven on gold side.\n", log_id(gold_wire->name), i);
continue; continue;
} }
if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); log(" Skipping signal bit %s [%d]: undriven on gate side.\n", log_id(gate_wire->name), i);
continue; continue;
} }
equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));

2
passes/fsm/fsm_detect.cc
View file

@ -61,7 +61,7 @@ ret_false:
if (recursion_monitor.count(cellport.first)) { if (recursion_monitor.count(cellport.first)) {
log_warning("logic loop in mux tree at signal %s in module %s.\n", log_warning("logic loop in mux tree at signal %s in module %s.\n",
log_signal(sig), RTLIL::id2cstr(module->name)); log_signal(sig), log_id(module->name));
goto ret_false; goto ret_false;
} }

28
passes/hierarchy/hierarchy.cc
View file

@ -87,7 +87,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
if (decl.index > 0) { if (decl.index > 0) {
portwidths[decl.portname] = max(portwidths[decl.portname], 1); portwidths[decl.portname] = max(portwidths[decl.portname], 1);
portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]); portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]);
log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname)); log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, log_id(decl.portname));
if (indices.count(decl.index) > ports.size()) if (indices.count(decl.index) > ports.size())
log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size())); log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size()));
if (indices.count(decl.index) == 0) if (indices.count(decl.index) == 0)
@ -108,10 +108,10 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
indices.erase(d.index); indices.erase(d.index);
ports[d.index-1] = d; ports[d.index-1] = d;
portwidths[d.portname] = max(portwidths[d.portname], 1); portwidths[d.portname] = max(portwidths[d.portname], 1);
log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname)); log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, log_id(d.portname));
goto found_matching_decl; goto found_matching_decl;
} }
log_error("Can't match port %s.\n", RTLIL::id2cstr(portname)); log_error("Can't match port %s.\n", log_id(portname));
found_matching_decl:; found_matching_decl:;
portnames.erase(portname); portnames.erase(portname);
} }
@ -133,9 +133,9 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
mod->fixup_ports(); mod->fixup_ports();
for (auto &para : parameters) for (auto &para : parameters)
log(" ignoring parameter %s.\n", RTLIL::id2cstr(para)); log(" ignoring parameter %s.\n", log_id(para));
log(" module %s created.\n", RTLIL::id2cstr(mod->name)); log(" module %s created.\n", log_id(mod->name));
} }
} }
@ -570,7 +570,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
int idx = it.second.first, num = it.second.second; int idx = it.second.first, num = it.second.second;
if (design->module(cell->type) == nullptr) if (design->module(cell->type) == nullptr)
log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_error("Array cell `%s.%s' of unknown type `%s'.\n", log_id(module->name), log_id(cell->name), log_id(cell->type));
RTLIL::Module *mod = design->module(cell->type); RTLIL::Module *mod = design->module(cell->type);
@ -586,12 +586,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
} }
} }
if (mod->wire(portname) == nullptr) if (mod->wire(portname) == nullptr)
log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", log_id(module->name), log_id(cell->name), log_id(conn.first));
int port_size = mod->wire(portname)->width; int port_size = mod->wire(portname)->width;
if (conn_size == port_size || conn_size == 0) if (conn_size == port_size || conn_size == 0)
continue; continue;
if (conn_size != port_size*num) if (conn_size != port_size*num)
log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", log_id(module->name), log_id(cell->name), log_id(conn.first));
conn.second = conn.second.extract(port_size*idx, port_size); conn.second = conn.second.extract(port_size*idx, port_size);
} }
} }
@ -1192,7 +1192,7 @@ struct HierarchyPass : public Pass {
if (read_id_num(p.first, &id)) { if (read_id_num(p.first, &id)) {
if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) { if (id <= 0 || id > GetSize(cell_mod->avail_parameters)) {
log(" Failed to map positional parameter %d of cell %s.%s (%s).\n", log(" Failed to map positional parameter %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(mod->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); id, log_id(mod->name), log_id(cell->name), log_id(cell->type));
} else { } else {
params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1])); params_rename.insert(std::make_pair(p.first, cell_mod->avail_parameters[id - 1]));
} }
@ -1214,7 +1214,7 @@ struct HierarchyPass : public Pass {
RTLIL::Module *module = work.first; RTLIL::Module *module = work.first;
RTLIL::Cell *cell = work.second; RTLIL::Cell *cell = work.second;
log("Mapping positional arguments of cell %s.%s (%s).\n", log("Mapping positional arguments of cell %s.%s (%s).\n",
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_id(module->name), log_id(cell->name), log_id(cell->type));
dict<RTLIL::IdString, RTLIL::SigSpec> new_connections; dict<RTLIL::IdString, RTLIL::SigSpec> new_connections;
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
int id; int id;
@ -1222,7 +1222,7 @@ struct HierarchyPass : public Pass {
std::pair<RTLIL::Module*,int> key(design->module(cell->type), id); std::pair<RTLIL::Module*,int> key(design->module(cell->type), id);
if (pos_map.count(key) == 0) { if (pos_map.count(key) == 0) {
log(" Failed to map positional argument %d of cell %s.%s (%s).\n", log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); id, log_id(module->name), log_id(cell->name), log_id(cell->type));
new_connections[conn.first] = conn.second; new_connections[conn.first] = conn.second;
} else } else
new_connections[pos_map.at(key)] = conn.second; new_connections[pos_map.at(key)] = conn.second;
@ -1256,7 +1256,7 @@ struct HierarchyPass : public Pass {
if (m == nullptr) if (m == nullptr)
log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n", log_error("Cell %s.%s (%s) has implicit port connections but the module it instantiates is unknown.\n",
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_id(module->name), log_id(cell->name), log_id(cell->type));
// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths // Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) { if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
@ -1285,11 +1285,11 @@ struct HierarchyPass : public Pass {
if (parent_wire == nullptr) if (parent_wire == nullptr)
log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n", log_error("No matching wire for implicit port connection `%s' of cell %s.%s (%s).\n",
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_id(wire->name), log_id(module->name), log_id(cell->name), log_id(cell->type));
if (parent_wire->width != wire->width) if (parent_wire->width != wire->width)
log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n", log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n",
parent_wire->width, wire->width, parent_wire->width, wire->width,
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_id(wire->name), log_id(module->name), log_id(cell->name), log_id(cell->type));
cell->setPort(wire->name, parent_wire); cell->setPort(wire->name, parent_wire);
} }
cell->attributes.erase(ID::wildcard_port_conns); cell->attributes.erase(ID::wildcard_port_conns);

2
passes/opt/opt_clean.cc
View file

@ -29,8 +29,6 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
struct keep_cache_t struct keep_cache_t
{ {
Design *design; Design *design;

18
passes/sat/expose.cc
View file

@ -471,7 +471,7 @@ struct ExposePass : public Pass {
{ {
if (!w->port_input) { if (!w->port_input) {
w->port_input = true; w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(w->name));
wire_map[w] = NEW_ID; wire_map[w] = NEW_ID;
} }
} }
@ -479,7 +479,7 @@ struct ExposePass : public Pass {
{ {
if (!w->port_output) { if (!w->port_output) {
w->port_output = true; w->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(w->name));
} }
if (flag_cut) { if (flag_cut) {
@ -555,7 +555,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width); RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
wire_q->port_input = true; wire_q->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(wire_q->name));
RTLIL::SigSig connect_q; RTLIL::SigSig connect_q;
for (size_t i = 0; i < wire_bits_vec.size(); i++) { for (size_t i = 0; i < wire_bits_vec.size(); i++) {
@ -569,12 +569,12 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width); RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width);
wire_d->port_output = true; wire_d->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(wire_d->name));
module->connect(RTLIL::SigSig(wire_d, info.sig_d)); module->connect(RTLIL::SigSig(wire_d, info.sig_d));
RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c"); RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c");
wire_c->port_output = true; wire_c->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(wire_c->name));
if (info.clk_polarity) { if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk)); module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else { } else {
@ -590,7 +590,7 @@ struct ExposePass : public Pass {
{ {
RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r"); RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r");
wire_r->port_output = true; wire_r->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(wire_r->name));
if (info.arst_polarity) { if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst)); module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else { } else {
@ -604,7 +604,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width); RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
wire_v->port_output = true; wire_v->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name)); log("New module port: %s/%s\n", log_id(module->name), log_id(wire_v->name));
module->connect(RTLIL::SigSig(wire_v, info.arst_value)); module->connect(RTLIL::SigSig(wire_v, info.arst_value));
} }
} }
@ -638,7 +638,7 @@ struct ExposePass : public Pass {
if (p->port_output) if (p->port_output)
w->port_input = true; w->port_input = true;
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); log("New module port: %s/%s (%s)\n", log_id(module->name), log_id(w->name), log_id(cell->type));
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (cell->hasPort(p->name)) if (cell->hasPort(p->name))
@ -660,7 +660,7 @@ struct ExposePass : public Pass {
if (ct.cell_output(cell->type, it.first)) if (ct.cell_output(cell->type, it.first))
w->port_input = true; w->port_input = true;
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); log("New module port: %s/%s (%s)\n", log_id(module->name), log_id(w->name), log_id(cell->type));
if (w->port_input) if (w->port_input)
module->connect(RTLIL::SigSig(it.second, w)); module->connect(RTLIL::SigSig(it.second, w));

10
passes/sat/freduce.cc
View file

@ -139,7 +139,7 @@ struct FindReducedInputs
if (ez_cells.count(drv.first) == 0) { if (ez_cells.count(drv.first) == 0) {
satgen.setContext(&sigmap, "A"); satgen.setContext(&sigmap, "A");
if (!satgen.importCell(drv.first)) if (!satgen.importCell(drv.first))
log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); log_error("Can't create SAT model for cell %s (%s)!\n", log_id(drv.first->name), log_id(drv.first->type));
satgen.setContext(&sigmap, "B"); satgen.setContext(&sigmap, "B");
if (!satgen.importCell(drv.first)) if (!satgen.importCell(drv.first))
log_abort(); log_abort();
@ -256,7 +256,7 @@ struct PerformReduction
std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out); std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
if (celldone.count(drv.first) == 0) { if (celldone.count(drv.first) == 0) {
if (!satgen.importCell(drv.first)) if (!satgen.importCell(drv.first))
log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type)); log_error("Can't create SAT model for cell %s (%s)!\n", log_id(drv.first->name), log_id(drv.first->type));
celldone.insert(drv.first); celldone.insert(drv.first);
} }
int max_child_depth = 0; int max_child_depth = 0;
@ -595,14 +595,14 @@ struct FreduceWorker
void dump() void dump()
{ {
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter); std::string filename = stringf("%s_%s_%05d.il", dump_prefix, log_id(module->name), reduce_counter);
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename); log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename);
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : ""));
} }
int run() int run()
{ {
log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name)); log("Running functional reduction on module %s:\n", log_id(module->name));
CellTypes ct; CellTypes ct;
ct.setup_internals(); ct.setup_internals();
@ -749,7 +749,7 @@ struct FreduceWorker
} }
} }
log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name)); log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, log_id(module->name));
return rewired_sigbits; return rewired_sigbits;
} }
}; };

2
passes/sat/miter.cc
View file

@ -128,7 +128,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name); log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name);
} }
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", log_id(miter_name), log_id(gold_name), log_id(gate_name));
RTLIL::Module *miter_module = new RTLIL::Module; RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->name = miter_name; miter_module->name = miter_name;

6
passes/sat/sat.cc
View file

@ -227,16 +227,16 @@ struct SatHelper
int import_cell_counter = 0; int import_cell_counter = 0;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (design->selected(module, cell)) { if (design->selected(module, cell)) {
// log("Import cell: %s\n", RTLIL::id2cstr(cell->name)); // log("Import cell: %s\n", log_id(cell->name));
if (satgen.importCell(cell, timestep)) { if (satgen.importCell(cell, timestep)) {
for (auto &p : cell->connections()) for (auto &p : cell->connections())
if (ct.cell_output(cell->type, p.first)) if (ct.cell_output(cell->type, p.first))
show_drivers.insert(sigmap(p.second), cell); show_drivers.insert(sigmap(p.second), cell);
import_cell_counter++; import_cell_counter++;
} else if (ignore_unknown_cells) } else if (ignore_unknown_cells)
log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_warning("Failed to import cell %s (type %s) to SAT database.\n", log_id(cell->name), log_id(cell->type));
else else
log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(cell->name), log_id(cell->type));
} }
log("Imported %d cells to SAT database.\n", import_cell_counter); log("Imported %d cells to SAT database.\n", import_cell_counter);

14
passes/techmap/iopadmap.cc
View file

@ -389,7 +389,7 @@ struct IopadmapPass : public Pass {
if (wire->port_input && !wire->port_output) { if (wire->port_input && !wire->port_output) {
if (inpad_celltype.empty()) { if (inpad_celltype.empty()) {
log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); log("Don't map input port %s.%s: Missing option -inpad.\n", log_id(module->name), log_id(wire->name));
continue; continue;
} }
celltype = inpad_celltype; celltype = inpad_celltype;
@ -398,7 +398,7 @@ struct IopadmapPass : public Pass {
} else } else
if (!wire->port_input && wire->port_output) { if (!wire->port_input && wire->port_output) {
if (outpad_celltype.empty()) { if (outpad_celltype.empty()) {
log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); log("Don't map output port %s.%s: Missing option -outpad.\n", log_id(module->name), log_id(wire->name));
continue; continue;
} }
celltype = outpad_celltype; celltype = outpad_celltype;
@ -407,7 +407,7 @@ struct IopadmapPass : public Pass {
} else } else
if (wire->port_input && wire->port_output) { if (wire->port_input && wire->port_output) {
if (inoutpad_celltype.empty()) { if (inoutpad_celltype.empty()) {
log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); log("Don't map inout port %s.%s: Missing option -inoutpad.\n", log_id(module->name), log_id(wire->name));
continue; continue;
} }
celltype = inoutpad_celltype; celltype = inoutpad_celltype;
@ -417,11 +417,11 @@ struct IopadmapPass : public Pass {
log_abort(); log_abort();
if (!flag_bits && wire->width != 1 && widthparam.empty()) { if (!flag_bits && wire->width != 1 && widthparam.empty()) {
log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", log_id(module->name), log_id(wire->name));
continue; continue;
} }
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype); log("Mapping port %s.%s using %s.\n", log_id(module->name), log_id(wire->name), celltype);
if (flag_bits) if (flag_bits)
{ {
@ -442,7 +442,7 @@ struct IopadmapPass : public Pass {
if (!widthparam.empty()) if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", log_id(wire->name), i));
cell->attributes[ID::keep] = RTLIL::Const(1); cell->attributes[ID::keep] = RTLIL::Const(1);
} }
} }
@ -465,7 +465,7 @@ struct IopadmapPass : public Pass {
if (!widthparam.empty()) if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(log_id(wire->name));
cell->attributes[ID::keep] = RTLIL::Const(1); cell->attributes[ID::keep] = RTLIL::Const(1);
} }

2
techlibs/ice40/ice40_braminit.cc
View file

@ -46,7 +46,7 @@ static void run_ice40_braminit(Module *module)
continue; continue;
/* Open file */ /* Open file */
log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file); log("Processing %s : %s\n", log_id(cell->name), init_file);
std::ifstream f; std::ifstream f;
f.open(init_file.c_str()); f.open(init_file.c_str());