Merge from upstream

tests/techmap/bug5574.ys

@@ -0,0 +1,11 @@
+# On Linux, with a spawned abc, this message is the error
+# otherwise the error is the failure to load the output.blif
+logger -expect log "ABC: Error: This command can only be applied to an AIG" 1
+logger -expect error "ABC" 1
+read_verilog << EOT
+module fuzz_mwoqk (input i0, output o0);
+  assign o0 = i0 ^ 1;
+endmodule
+EOT
+synth
+abc -script +resub,-K,8;

tests/techmap/lut2mux.ys

@@ -0,0 +1,42 @@
+# Test lut2mux pass using a directly constructed $lut (avoids frontend/synth differences in test-verific)
+
+read_rtlil << EOT
+module \top
+  wire width 2 input 1 \a
+  wire width 1 output 2 \y
+  cell $lut \u_lut
+    parameter \WIDTH 2
+    parameter \LUT 4'0110
+    connect \A \a
+    connect \Y \y
+  end
+end
+EOT
+
+select -assert-count 1 t:$lut
+
+# default mode -> gate-level $_MUX_
+design -save gold
+lut2mux
+rename \top \gate
+select -assert-count 3 gate/t:$_MUX_
+select -assert-count 0 gate/t:$mux
+select -assert-count 0 gate/t:$lut
+
+# -word mode -> word-level $mux
+design -copy-from gold -as top \top
+select -none
+select top
+lut2mux -word
+select -clear
+rename \top \word
+select -assert-count 3 word/t:$mux
+select -assert-count 0 word/t:$_MUX_
+select -assert-count 0 gate/t:$lut
+
+# equivalence
+equiv_make \gate \word equiv
+hierarchy -top equiv
+equiv_simple
+equiv_induct
+equiv_status -assert

tests/techmap/module_not_derived.ys

@@ -0,0 +1,31 @@
+# Test 1: internal cells from alumacc/techmap must not keep module_not_derived.
+read_verilog <<EOF_VERILOG
+module top(a, b, y);
+  input wire [7:0] a;
+  input wire [7:0] b;
+  output wire [7:0] y;
+  assign y = a + b;
+endmodule
+EOF_VERILOG
+
+prep
+alumacc
+techmap -max_iter 1
+
+select -assert-any t:$lcu
+select -assert-count 0 t:$lcu a:module_not_derived %i
+
+design -reset
+# Test 2: public module instances should still keep module_not_derived.
+read_verilog <<EOF_VERILOG
+module mycell(input a, output y);
+	assign y = a;
+endmodule
+
+module top(input a, output y);
+	mycell u0(.a(a), .y(y));
+endmodule
+EOF_VERILOG
+
+hierarchy -top top
+select -assert-any t:mycell a:module_not_derived %i