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https://github.com/YosysHQ/yosys
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Merge from upstream
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commit
26f5ff3d74
20 changed files with 1231 additions and 38 deletions
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@ -2085,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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check_unique_id(current_module, id, this, "cell");
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RTLIL::Cell *cell = current_module->addCell(id, "");
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set_src_attr(cell, this);
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// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
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cell->set_bool_attribute(ID::module_not_derived);
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for (auto it = children.begin(); it != children.end(); it++) {
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auto* child = it->get();
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@ -2149,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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}
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log_abort();
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}
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// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
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if (cell->type.isPublic())
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cell->set_bool_attribute(ID::module_not_derived);
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for (auto &attr : attributes) {
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if (attr.second->type != AST_CONSTANT)
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input_error("Attribute `%s' with non-constant value.\n", attr.first);
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@ -470,6 +470,27 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
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continue;
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}
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if (!strcmp(cmd, ".gateinit"))
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{
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char *p = strtok(NULL, " \t\r\n");
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if (p == NULL)
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goto error;
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char *n = strtok(p, "=");
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char *init = strtok(NULL, "=");
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if (n == NULL || init == NULL)
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goto error;
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if (init[0] != '0' && init[0] != '1')
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goto error;
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if (blif_wire(n)->attributes.find(ID::init) == blif_wire(n)->attributes.end())
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blif_wire(n)->attributes.emplace(ID::init, Const(init[0] == '1' ? 1 : 0, 1));
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else
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blif_wire(n)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
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continue;
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}
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if (!strcmp(cmd, ".names"))
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{
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char *p;
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