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Fix for A_WIDTH == 2 but B_WIDTH==3

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This commit is contained in:
Eddie Hung 2019-04-22 17:58:28 -07:00
parent 1fa2c36fbd
commit 26e461f47d
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/cells_map.v
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@ -179,7 +179,7 @@ module \$shiftx (A, B, Y);
assign A_i[i] = A[i*2];
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
end
else if (B_WIDTH < 3) begin
else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin
wire _TECHMAP_FAIL_ = 1;
end
else if (B_WIDTH == 3) begin