mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-07 19:51:23 +00:00
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
This commit is contained in:
Eddie Hung
commit
26cb3e7afc
56 changed files with 763 additions and 172 deletions
|
|
@ -223,6 +223,37 @@ struct statdata_t
|
|||
log("\n");
|
||||
log(" Estimated number of LCs: %10d\n", lc_cnt);
|
||||
}
|
||||
|
||||
if (tech == "cmos")
|
||||
{
|
||||
int tran_cnt = 0;
|
||||
bool tran_cnt_exact = true;
|
||||
|
||||
for (auto it : num_cells_by_type) {
|
||||
auto ctype = it.first;
|
||||
auto cnum = it.second;
|
||||
|
||||
if (ctype == "$_NOT_")
|
||||
tran_cnt += 2*cnum;
|
||||
else if (ctype.in("$_NAND_", "$_NOR_"))
|
||||
tran_cnt += 4*cnum;
|
||||
else if (ctype.in("$_AOI3_", "$_OAI3_"))
|
||||
tran_cnt += 6*cnum;
|
||||
else if (ctype.in("$_AOI4_", "$_OAI4_"))
|
||||
tran_cnt += 8*cnum;
|
||||
else if (ctype.in("$_NMUX_"))
|
||||
tran_cnt += 10*cnum;
|
||||
else if (ctype.in("$_MUX_", "$_XOR_", "$_XNOR_"))
|
||||
tran_cnt += 12*cnum;
|
||||
else if (ctype.in("$_DFF_P_", "$_DFF_N_"))
|
||||
tran_cnt += 16*cnum;
|
||||
else
|
||||
tran_cnt_exact = false;
|
||||
}
|
||||
|
||||
log("\n");
|
||||
log(" Estimated number of transistors: %10d%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -286,7 +317,7 @@ struct StatPass : public Pass {
|
|||
log("\n");
|
||||
log(" -tech <technology>\n");
|
||||
log(" print area estemate for the specified technology. Currently supported\n");
|
||||
log(" values for <technology>: xilinx\n");
|
||||
log(" values for <technology>: xilinx, cmos\n");
|
||||
log("\n");
|
||||
log(" -width\n");
|
||||
log(" annotate internal cell types with their word width.\n");
|
||||
|
|
@ -330,7 +361,7 @@ struct StatPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (techname != "" && techname != "xilinx")
|
||||
if (techname != "" && techname != "xilinx" && techname != "cmos")
|
||||
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
|
||||
|
||||
for (auto mod : design->selected_modules())
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ struct OptLutWorker
|
|||
}
|
||||
}
|
||||
|
||||
log("Number of LUTs: %8zu\n", luts.size());
|
||||
log("Number of LUTs: %8d\n", GetSize(luts));
|
||||
for (int arity = 1; arity <= max_arity; arity++)
|
||||
{
|
||||
if (arity_counts[arity])
|
||||
|
|
@ -351,14 +351,14 @@ struct OptLutWorker
|
|||
|
||||
int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
|
||||
if (lutA_dlogic_inputs.size())
|
||||
log_debug(" Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
|
||||
log_debug(" Cell A is a %d-LUT with %d dedicated connections. ", lutA_arity, GetSize(lutA_dlogic_inputs));
|
||||
else
|
||||
log_debug(" Cell A is a %d-LUT. ", lutA_arity);
|
||||
if (lutB_dlogic_inputs.size())
|
||||
log_debug("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
|
||||
log_debug("Cell B is a %d-LUT with %d dedicated connections.\n", lutB_arity, GetSize(lutB_dlogic_inputs));
|
||||
else
|
||||
log_debug("Cell B is a %d-LUT.\n", lutB_arity);
|
||||
log_debug(" Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
|
||||
log_debug(" Cells share %d input(s) and can be merged into one %d-LUT.\n", GetSize(common_inputs), lutM_arity);
|
||||
|
||||
const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
|
||||
int combine_mask = 0;
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ struct RmportsPassPass : public Pass {
|
|||
wire->port_output = false;
|
||||
wire->port_id = 0;
|
||||
}
|
||||
log("Removed %zu unused ports.\n", unused_ports.size());
|
||||
log("Removed %d unused ports.\n", GetSize(unused_ports));
|
||||
|
||||
// Re-number all of the wires that DO have ports still on them
|
||||
for(size_t i=0; i<module->ports.size(); i++)
|
||||
|
|
|
|||
|
|
@ -82,14 +82,23 @@ struct PruneWorker
|
|||
if (root) {
|
||||
bool promotable = true;
|
||||
for (auto &bit : lhs) {
|
||||
if (bit.wire && affected[bit]) {
|
||||
if (bit.wire && affected[bit] && !assigned[bit]) {
|
||||
promotable = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (promotable) {
|
||||
RTLIL::SigSpec rhs = sigmap(it->second);
|
||||
RTLIL::SigSig conn;
|
||||
for (int i = 0; i < GetSize(lhs); i++) {
|
||||
RTLIL::SigBit lhs_bit = lhs[i];
|
||||
if (lhs_bit.wire && !assigned[lhs_bit]) {
|
||||
conn.first.append_bit(lhs_bit);
|
||||
conn.second.append(rhs.extract(i));
|
||||
}
|
||||
}
|
||||
promoted_count++;
|
||||
module->connect(*it);
|
||||
module->connect(conn);
|
||||
remove.insert(*it);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <cctype>
|
||||
#include <cerrno>
|
||||
#include <sstream>
|
||||
#include <climits>
|
||||
|
|
@ -81,6 +82,7 @@ enum class gate_type_t {
|
|||
G_ANDNOT,
|
||||
G_ORNOT,
|
||||
G_MUX,
|
||||
G_NMUX,
|
||||
G_AOI3,
|
||||
G_OAI3,
|
||||
G_AOI4,
|
||||
|
|
@ -111,7 +113,7 @@ std::vector<gate_t> signal_list;
|
|||
std::map<RTLIL::SigBit, int> signal_map;
|
||||
std::map<RTLIL::SigBit, RTLIL::State> signal_init;
|
||||
pool<std::string> enabled_gates;
|
||||
bool recover_init;
|
||||
bool recover_init, cmos_cost;
|
||||
|
||||
bool clk_polarity, en_polarity;
|
||||
RTLIL::SigSpec clk_sig, en_sig;
|
||||
|
|
@ -257,7 +259,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
|
|||
return;
|
||||
}
|
||||
|
||||
if (cell->type == "$_MUX_")
|
||||
if (cell->type.in("$_MUX_", "$_NMUX_"))
|
||||
{
|
||||
RTLIL::SigSpec sig_a = cell->getPort("\\A");
|
||||
RTLIL::SigSpec sig_b = cell->getPort("\\B");
|
||||
|
|
@ -273,7 +275,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
|
|||
int mapped_b = map_signal(sig_b);
|
||||
int mapped_s = map_signal(sig_s);
|
||||
|
||||
map_signal(sig_y, G(MUX), mapped_a, mapped_b, mapped_s);
|
||||
map_signal(sig_y, cell->type == "$_MUX_" ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
|
||||
|
||||
module->remove(cell);
|
||||
return;
|
||||
|
|
@ -885,6 +887,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
|
||||
fprintf(f, "1-0 1\n");
|
||||
fprintf(f, "-11 1\n");
|
||||
} else if (si.type == G(NMUX)) {
|
||||
fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
|
||||
fprintf(f, "0-0 1\n");
|
||||
fprintf(f, "-01 1\n");
|
||||
} else if (si.type == G(AOI3)) {
|
||||
fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
|
||||
fprintf(f, "-00 1\n");
|
||||
|
|
@ -925,46 +931,52 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
{
|
||||
log_header(design, "Executing ABC.\n");
|
||||
|
||||
auto cell_cost = [](IdString cell_type) {
|
||||
return get_cell_cost(cell_type, dict<RTLIL::IdString, RTLIL::Const>(), nullptr, nullptr, cmos_cost);
|
||||
};
|
||||
|
||||
buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
|
||||
f = fopen(buffer.c_str(), "wt");
|
||||
if (f == NULL)
|
||||
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
|
||||
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
|
||||
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
|
||||
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
|
||||
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
|
||||
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost("$_BUF_"));
|
||||
fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost("$_NOT_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("AND"))
|
||||
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
|
||||
fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost("$_AND_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("NAND"))
|
||||
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
|
||||
fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_NAND_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("OR"))
|
||||
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
|
||||
fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost("$_OR_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("NOR"))
|
||||
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
|
||||
fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_NOR_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("XOR"))
|
||||
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
|
||||
fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_XOR_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("XNOR"))
|
||||
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
|
||||
fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_XNOR_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
|
||||
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
|
||||
fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_ANDNOT_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
|
||||
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
|
||||
fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_ORNOT_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("AOI3"))
|
||||
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
|
||||
fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_AOI3_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("OAI3"))
|
||||
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
|
||||
fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_OAI3_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("AOI4"))
|
||||
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
|
||||
fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_AOI4_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("OAI4"))
|
||||
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
|
||||
fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost("$_OAI4_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("MUX"))
|
||||
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_MUX_"));
|
||||
if (enabled_gates.empty() || enabled_gates.count("NMUX"))
|
||||
fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost("$_NMUX_"));
|
||||
if (map_mux4)
|
||||
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost("$_MUX_"));
|
||||
if (map_mux8)
|
||||
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost("$_MUX_"));
|
||||
if (map_mux16)
|
||||
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
|
||||
fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost("$_MUX_"));
|
||||
fclose(f);
|
||||
|
||||
if (!lut_costs.empty()) {
|
||||
|
|
@ -1065,8 +1077,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
design->select(module, cell);
|
||||
continue;
|
||||
}
|
||||
if (c->type == "\\MUX") {
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
|
||||
if (c->type == "\\MUX" || c->type == "\\NMUX") {
|
||||
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
|
||||
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
|
||||
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
|
||||
cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
|
||||
|
|
@ -1406,11 +1418,12 @@ struct AbcPass : public Pass {
|
|||
log("\n");
|
||||
log(" The following aliases can be used to reference common sets of gate types:\n");
|
||||
log(" simple: AND OR XOR MUX\n");
|
||||
log(" cmos2: NAND NOR\n");
|
||||
log(" cmos3: NAND NOR AOI3 OAI3\n");
|
||||
log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
|
||||
log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
|
||||
log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
|
||||
log(" cmos2: NAND NOR\n");
|
||||
log(" cmos3: NAND NOR AOI3 OAI3\n");
|
||||
log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
|
||||
log(" cmos: NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR\n");
|
||||
log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
|
||||
log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
|
||||
log("\n");
|
||||
log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
|
||||
log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
|
||||
|
|
@ -1488,6 +1501,7 @@ struct AbcPass : public Pass {
|
|||
map_mux8 = false;
|
||||
map_mux16 = false;
|
||||
enabled_gates.clear();
|
||||
cmos_cost = false;
|
||||
|
||||
#ifdef _WIN32
|
||||
#ifndef ABCEXTERNAL
|
||||
|
|
@ -1628,11 +1642,15 @@ struct AbcPass : public Pass {
|
|||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos2") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos3") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
gate_list.push_back("AOI3");
|
||||
|
|
@ -1640,6 +1658,8 @@ struct AbcPass : public Pass {
|
|||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos4") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
gate_list.push_back("AOI3");
|
||||
|
|
@ -1648,6 +1668,21 @@ struct AbcPass : public Pass {
|
|||
gate_list.push_back("OAI4");
|
||||
goto ok_alias;
|
||||
}
|
||||
if (g == "cmos") {
|
||||
if (!remove_gates)
|
||||
cmos_cost = true;
|
||||
gate_list.push_back("NAND");
|
||||
gate_list.push_back("NOR");
|
||||
gate_list.push_back("AOI3");
|
||||
gate_list.push_back("OAI3");
|
||||
gate_list.push_back("AOI4");
|
||||
gate_list.push_back("OAI4");
|
||||
gate_list.push_back("NMUX");
|
||||
gate_list.push_back("MUX");
|
||||
gate_list.push_back("XOR");
|
||||
gate_list.push_back("XNOR");
|
||||
goto ok_alias;
|
||||
}
|
||||
if (g == "gates") {
|
||||
gate_list.push_back("AND");
|
||||
gate_list.push_back("NAND");
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ struct ExtractFaWorker
|
|||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
|
||||
"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_",
|
||||
"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", "$_NMUX_",
|
||||
"$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
|
||||
{
|
||||
SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
|
||||
|
|
|
|||
|
|
@ -783,7 +783,7 @@ struct FlowmapWorker
|
|||
int depth = 0;
|
||||
for (auto label : labels)
|
||||
depth = max(depth, label.second);
|
||||
log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
|
||||
log("Mapped to %d LUTs with maximum depth %d.\n", GetSize(lut_nodes), depth);
|
||||
|
||||
if (debug)
|
||||
{
|
||||
|
|
@ -1195,7 +1195,7 @@ struct FlowmapWorker
|
|||
|
||||
bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
|
||||
{
|
||||
size_t initial_count = lut_nodes.size();
|
||||
int initial_count = GetSize(lut_nodes);
|
||||
|
||||
for (auto node : lut_nodes)
|
||||
{
|
||||
|
|
@ -1215,7 +1215,7 @@ struct FlowmapWorker
|
|||
|
||||
if (potentials.empty())
|
||||
{
|
||||
log(" Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
|
||||
log(" Relaxed to %d (+%d) LUTs.\n", GetSize(lut_nodes), GetSize(lut_nodes) - initial_count);
|
||||
if (!first && break_num == 1)
|
||||
{
|
||||
log(" Design fully relaxed.\n");
|
||||
|
|
@ -1419,9 +1419,9 @@ struct FlowmapWorker
|
|||
lut_area += lut_table.size();
|
||||
|
||||
if ((int)input_nodes.size() >= minlut)
|
||||
log(" Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
|
||||
log(" Packed into a %d-LUT %s.%s.\n", GetSize(input_nodes), log_id(module), log_id(lut));
|
||||
else
|
||||
log(" Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
|
||||
log(" Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", GetSize(input_nodes), log_id(module), log_id(lut), minlut);
|
||||
}
|
||||
|
||||
for (auto node : mapped_nodes)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue