diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc
index 61794f539..a9f2671fc 100644
--- a/techlibs/xilinx/xilinx_dsp.cc
+++ b/techlibs/xilinx/xilinx_dsp.cc
@@ -73,10 +73,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
 		if (!cell->type.in(ID($add), ID($sub)))
 			continue;
 		SigSpec Y = cell->getPort(ID::Y);
-		if (!Y.is_chunk() || Y.is_wire())
+		if (!Y.is_chunk())
 			continue;
-		Wire* wire = (*sigmap)(Y).as_wire();
-		if (!wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
+		if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
 			continue;
 		if (GetSize(Y) > 25)
 			continue;