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https://github.com/YosysHQ/yosys
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Add mul2dsp multiplier splitting rule and ECP5 mapping
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
c35023d0bf
commit
269ff450f5
5 changed files with 280 additions and 2 deletions
237
techlibs/common/mul2dsp.v
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237
techlibs/common/mul2dsp.v
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// From Eddie Hung
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// extracted from: https://github.com/eddiehung/vtr-with-yosys/blob/vtr7-with-yosys/vtr_flow/misc/yosys_models.v#L220
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// revised by Andre DeHon
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// further revised by David Shah
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`ifndef DSP_A_MAXWIDTH
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`define DSP_A_MAXWIDTH 18
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`endif
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`ifndef DSP_A_MAXWIDTH
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`define DSP_B_MAXWIDTH 25
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`endif
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`ifndef ADDER_MINWIDTH
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`define ADDER_MINWIDTH AAA
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`endif
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`ifndef DSP_NAME
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`define DSP_NAME M18x25
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`endif
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`define MAX(a,b) (a > b ? a : b)
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`define MIN(a,b) (a < b ? a : b)
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(* techmap_celltype = "$mul" *)
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module \$mul (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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generate
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if (A_WIDTH<B_WIDTH) begin
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generate
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) mul_slice (
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.A(A),
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.B(B),
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.Y(Y[Y_WIDTH-1:0])
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);
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endgenerate
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end
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else begin
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generate
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\$__mul_gen #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) mul_slice (
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.A(B),
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.B(A),
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.Y(Y[Y_WIDTH-1:0])
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);
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endgenerate
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end
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endgenerate
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endmodule
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module \$__mul_gen (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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generate
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if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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localparam n_floored = A_WIDTH/`DSP_A_MAXWIDTH;
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localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0);
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wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1];
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wire [Y_WIDTH-1:0] partial_sum [n-2:0];
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH)
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) mul_slice_first (
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.A(A[`DSP_A_MAXWIDTH-1:0]),
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.B(B),
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.Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0])
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);
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assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0;
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genvar i;
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generate
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH)
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) mul_slice (
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.A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]),
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.B(B),
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.Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0])
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);
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//assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1];
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assign partial_sum[i] = {
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partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]
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+ partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)],
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partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0]
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};
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end
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endgenerate
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH),
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) mul_slice_last (
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.A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]),
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.B(B),
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.Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0])
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);
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//assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2];
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assign Y = {
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partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0]
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+ partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)],
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partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0]
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};
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end
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else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
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localparam n_floored = B_WIDTH/`DSP_B_MAXWIDTH;
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localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0);
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wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1];
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wire [Y_WIDTH-1:0] partial_sum [n-2:0];
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH)
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) mul_first (
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.A(A),
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.B(B[`DSP_B_MAXWIDTH-1:0]),
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.Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0])
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);
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assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0;
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genvar i;
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generate
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for (i = 1; i < n-1; i=i+1) begin:slice
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(`DSP_B_MAXWIDTH),
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.Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH)
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) mul (
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.A(A),
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.B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]),
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.Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0])
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);
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//assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1];
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// was:
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//assign partial_sum[i] = {
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// partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],
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// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)],
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// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0]
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assign partial_sum[i] = {
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partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]
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+ partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)],
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partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0]
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};
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end
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endgenerate
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\$__mul_gen #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH),
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.Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)
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) mul_last (
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.A(A),
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.B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]),
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.Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0])
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);
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// AMD: this came comment out -- looks closer to right answer
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//assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2];
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// was (looks broken)
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//assign Y = {
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// partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],
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// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)],
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// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0]
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assign Y = {
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partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]
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+ partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)],
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partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0]
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};
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end
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else begin
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wire [A_WIDTH+B_WIDTH-1:0] out;
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wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy;
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wire Asign, Bsign;
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assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
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assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0);
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`DSP_NAME _TECHMAP_REPLACE_ (
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.A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }),
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.B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }),
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.OUT({dummy, out})
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);
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if (Y_WIDTH < A_WIDTH+B_WIDTH)
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assign Y = out[Y_WIDTH-1:0];
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else begin
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wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0);
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assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] };
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end
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end
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endgenerate
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endmodule
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