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Add VerificClocking class and refactor Verific DFF handling

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-04 13:48:53 +01:00
parent ae4e204c76
commit 261cf706f4
3 changed files with 197 additions and 127 deletions
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17
frontends/verific/verific.h
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@ -29,11 +29,22 @@ extern pool<int> verific_sva_prims;
struct VerificImporter;
struct VerificClockEdge {
struct VerificClocking {
RTLIL::Module *module = nullptr;
Verific::Net *clock_net = nullptr;
Verific::Net *enable_net = nullptr;
Verific::Net *disable_net = nullptr;
Verific::Net *body_net = nullptr;
SigBit clock_sig = State::Sx;
bool posedge = false;
VerificClockEdge(VerificImporter *importer, Verific::Instance *inst);
SigBit enable_sig = State::S1;
SigBit disable_sig = State::S0;
bool posedge = true;
VerificClocking() { }
VerificClocking(VerificImporter *importer, Verific::Net *net);
RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const());
RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value);
RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q);
};
struct VerificImporter