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https://github.com/YosysHQ/yosys
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Add VerificClocking class and refactor Verific DFF handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
ae4e204c76
commit
261cf706f4
3 changed files with 197 additions and 127 deletions
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@ -277,16 +277,18 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
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if (inst->Type() == PRIM_DFFRS)
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{
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VerificClocking clocking(this, inst->GetClock());
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log_assert(clocking.disable_sig == State::S0);
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log_assert(clocking.body_net == nullptr);
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if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
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module->addDffGate(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
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clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
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else if (inst->GetSet()->IsGnd())
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module->addAdffGate(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetReset()),
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net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), false);
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clocking.addAdff(inst_name, net_map_at(inst->GetReset()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), State::S0);
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else if (inst->GetReset()->IsGnd())
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module->addAdffGate(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetSet()),
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net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), true);
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clocking.addAdff(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), State::S1);
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else
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module->addDffsrGate(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
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clocking.addDffsr(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
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net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
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return true;
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}
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@ -358,16 +360,18 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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if (inst->Type() == PRIM_DFFRS)
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{
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VerificClocking clocking(this, inst->GetClock());
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log_assert(clocking.disable_sig == State::S0);
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log_assert(clocking.body_net == nullptr);
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if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
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module->addDff(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
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clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
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else if (inst->GetSet()->IsGnd())
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module->addAdff(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetReset()),
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net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S0);
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clocking.addAdff(inst_name, net_map_at(inst->GetReset()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S0);
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else if (inst->GetReset()->IsGnd())
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module->addAdff(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetSet()),
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net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S1);
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clocking.addAdff(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S1);
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else
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module->addDffsr(inst_name, net_map_at(inst->GetClock()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
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clocking.addDffsr(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
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net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
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return true;
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}
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@ -594,13 +598,20 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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return true;
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}
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if (inst->Type() == OPER_WIDE_DFFRS) {
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if (inst->Type() == OPER_WIDE_DFFRS)
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{
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VerificClocking clocking(this, inst->GetClock());
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log_assert(clocking.disable_sig == State::S0);
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log_assert(clocking.body_net == nullptr);
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RTLIL::SigSpec sig_set = operatorInport(inst, "set");
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RTLIL::SigSpec sig_reset = operatorInport(inst, "reset");
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if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
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module->addDff(inst_name, net_map_at(inst->GetClock()), IN, OUT);
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clocking.addDff(inst_name, IN, OUT);
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else
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module->addDffsr(inst_name, net_map_at(inst->GetClock()), sig_set, sig_reset, IN, OUT);
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clocking.addDffsr(inst_name, sig_set, sig_reset, IN, OUT);
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return true;
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}
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@ -1097,7 +1108,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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if (inst->Type() == OPER_SVA_STABLE)
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{
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VerificClockEdge clock_edge(this, inst->GetInput2Bit(0)->Driver());
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VerificClocking clocking(this, inst->GetInput2Bit(0));
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log_assert(inst->Input1Size() == inst->OutputSize());
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@ -1110,13 +1121,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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}
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if (verific_verbose) {
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
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log(" XNOR with A=%s, B=%s, Y=%s.\n",
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log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
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}
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module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
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clocking.addDff(NEW_ID, sig_d, sig_q);
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module->addXnor(NEW_ID, sig_d, sig_q, sig_o);
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if (!mode_keep)
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@ -1125,20 +1136,20 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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if (inst->Type() == PRIM_SVA_STABLE)
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{
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VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
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VerificClocking clocking(this, inst->GetInput2());
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SigSpec sig_d = net_map_at(inst->GetInput1());
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SigSpec sig_o = net_map_at(inst->GetOutput());
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SigSpec sig_q = module->addWire(NEW_ID);
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if (verific_verbose) {
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
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log(" XNOR with A=%s, B=%s, Y=%s.\n",
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log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
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}
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module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
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clocking.addDff(NEW_ID, sig_d, sig_q);
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module->addXnor(NEW_ID, sig_d, sig_q, sig_o);
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if (!mode_keep)
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@ -1147,16 +1158,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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if (inst->Type() == PRIM_SVA_PAST)
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{
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VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
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VerificClocking clocking(this, inst->GetInput2());
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SigBit sig_d = net_map_at(inst->GetInput1());
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SigBit sig_q = net_map_at(inst->GetOutput());
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if (verific_verbose)
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
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past_ffs.insert(module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge));
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past_ffs.insert(clocking.addDff(NEW_ID, sig_d, sig_q));
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if (!mode_keep)
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continue;
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@ -1164,17 +1175,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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if ((inst->Type() == PRIM_SVA_ROSE || inst->Type() == PRIM_SVA_FELL))
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{
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VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
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VerificClocking clocking(this, inst->GetInput2());
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SigBit sig_d = net_map_at(inst->GetInput1());
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SigBit sig_o = net_map_at(inst->GetOutput());
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SigBit sig_q = module->addWire(NEW_ID);
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if (verific_verbose)
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
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log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
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log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
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module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
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clocking.addDff(NEW_ID, sig_d, sig_q);
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module->addEq(NEW_ID, {sig_q, sig_d}, Const(inst->Type() == PRIM_SVA_ROSE ? 1 : 2, 2), sig_o);
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if (!mode_keep)
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@ -1259,26 +1270,130 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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// ==================================================================
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VerificClockEdge::VerificClockEdge(VerificImporter *importer, Instance *inst)
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VerificClocking::VerificClocking(VerificImporter *importer, Net *net)
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{
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module = importer->module;
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log_assert(importer != nullptr);
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log_assert(inst != nullptr);
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log_assert(net != nullptr);
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// SVA posedge/negedge
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if (inst->Type() == PRIM_SVA_POSEDGE)
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Instance *inst = net->Driver();
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if (inst != nullptr && inst->Type() == PRIM_SVA_AT)
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{
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clock_net = inst->GetInput();
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posedge = true;
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net = inst->GetInput1();
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body_net = inst->GetInput2();
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Instance *driver = clock_net->Driver();
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if (!clock_net->IsMultipleDriven() && driver && driver->Type() == PRIM_INV) {
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clock_net = driver->GetInput();
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posedge = false;
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inst = net->Driver();
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Instance *body_inst = body_net->Driver();
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if (body_inst != nullptr && body_inst->Type() == PRIM_SVA_DISABLE_IFF) {
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disable_net = body_inst->GetInput1();
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disable_sig = importer->net_map_at(disable_net);
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body_net = body_inst->GetInput2();
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}
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clock_sig = importer->net_map_at(clock_net);
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return;
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}
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if (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE)
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{
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net = inst->GetInput();
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inst = net->Driver();;
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}
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if (inst != nullptr && inst->Type() == PRIM_INV)
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{
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net = inst->GetInput();
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inst = net->Driver();;
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posedge = false;
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}
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// Detect clock-enable circuit
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do {
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if (inst == nullptr || inst->Type() != PRIM_AND)
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break;
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Net *net_dlatch = inst->GetInput1();
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Instance *inst_dlatch = net_dlatch->Driver();
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if (inst_dlatch == nullptr || inst_dlatch->Type() != PRIM_DLATCHRS)
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break;
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if (!inst_dlatch->GetSet()->IsGnd() || !inst_dlatch->GetReset()->IsGnd())
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break;
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Net *net_enable = inst_dlatch->GetInput();
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Net *net_not_clock = inst_dlatch->GetControl();
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if (net_enable == nullptr || net_not_clock == nullptr)
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break;
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Instance *inst_not_clock = net_not_clock->Driver();
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if (inst_not_clock == nullptr || inst_not_clock->Type() != PRIM_INV)
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break;
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Net *net_clock1 = inst_not_clock->GetInput();
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Net *net_clock2 = inst->GetInput2();
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if (net_clock1 == nullptr || net_clock1 != net_clock2)
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break;
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enable_net = net_enable;
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enable_sig = importer->net_map_at(enable_net);
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net = net_clock1;
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inst = net->Driver();;
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} while (0);
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clock_net = net;
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clock_sig = importer->net_map_at(clock_net);
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}
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Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value)
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{
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log_assert(GetSize(sig_d) == GetSize(sig_q));
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if (GetSize(init_value) != 0) {
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log_assert(GetSize(sig_q) == GetSize(init_value));
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if (sig_q.is_wire()) {
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sig_q.as_wire()->attributes["\\init"] = init_value;
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} else {
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Wire *w = module->addWire(NEW_ID, GetSize(sig_q));
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w->attributes["\\init"] = init_value;
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module->connect(sig_q, w);
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sig_q = w;
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}
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}
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if (enable_sig != State::S1)
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sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
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if (disable_sig != State::S0) {
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log_assert(GetSize(sig_q) == GetSize(init_value));
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return module->addAdff(name, clock_sig, disable_sig, sig_d, sig_q, init_value, posedge);
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}
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return module->addDff(name, clock_sig, sig_d, sig_q, posedge);
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}
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Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value)
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{
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log_assert(disable_sig == State::S0);
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if (enable_sig != State::S1)
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sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
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return module->addAdff(name, clock_sig, sig_arst, sig_d, sig_q, arst_value, posedge);
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}
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Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q)
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{
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log_assert(disable_sig == State::S0);
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if (enable_sig != State::S1)
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sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig);
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return module->addDffsr(name, clock_sig, sig_set, sig_clr, sig_d, sig_q, posedge);
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}
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// ==================================================================
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