mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 01:54:10 +00:00
Code Activity

Merge pull request #4702 from povik/cellmatch-derive-luts

Browse source 
Document `cellmatch -derive_luts` option
This commit is contained in:
Lofty 2024-11-04 15:38:04 +00:00 committed by GitHub
parent b2d78589e2 d752ca4847
commit 2610ccb8fa
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
3 changed files with 21 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
passes/techmap/cellmatch.cc
View file

@ -155,18 +155,22 @@ struct CellmatchPass : Pass {
log("equivalent as long as their truth tables are identical upto a permutation of\n"); log("equivalent as long as their truth tables are identical upto a permutation of\n");
log("inputs and outputs. The supported number of inputs is limited to 6.\n"); log("inputs and outputs. The supported number of inputs is limited to 6.\n");
log("\n"); log("\n");
log(" cellmatch -derive_luts [module selection]\n");
log("\n");
log("For every port in each selected module, characterize its combinational\n");
log("function with a 'lut' attribute if possible.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *d) override void execute(std::vector<std::string> args, RTLIL::Design *d) override
{ {
log_header(d, "Executing CELLMATCH pass. (match cells)\n"); log_header(d, "Executing CELLMATCH pass. (match cells)\n");
size_t argidx; size_t argidx;
bool lut_attrs = false; bool derive_luts = false;
Design *lib = NULL; Design *lib = NULL;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-lut_attrs") { if (args[argidx] == "-derive_luts") {
// an undocumented debugging option derive_luts = true;
lut_attrs = true;
} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) { } else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
if (!saved_designs.count(args[++argidx])) if (!saved_designs.count(args[++argidx]))
log_cmd_error("No design '%s' found!\n", args[argidx].c_str()); log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
@ -177,8 +181,8 @@ struct CellmatchPass : Pass {
} }
extra_args(args, argidx, d); extra_args(args, argidx, d);
if (!lib && !lut_attrs) if (!lib && !derive_luts)
log_cmd_error("Missing required -lib option.\n"); log_cmd_error("Missing required -lib or -derive_luts option.\n");
struct Target { struct Target {
Module *module; Module *module;
@ -210,7 +214,7 @@ struct CellmatchPass : Pass {
r.first->second = new Design; r.first->second = new Design;
Design *map_design = r.first->second; Design *map_design = r.first->second;
for (auto m : d->selected_whole_modules_warn()) { for (auto m : d->selected_whole_modules_warn(/* visit whiteboxes */derive_luts)) {
std::vector<uint64_t> luts; std::vector<uint64_t> luts;
if (!derive_module_luts(m, luts)) if (!derive_module_luts(m, luts))
continue; continue;
@ -218,7 +222,7 @@ struct CellmatchPass : Pass {
SigSpec inputs = module_inputs(m); SigSpec inputs = module_inputs(m);
SigSpec outputs = module_outputs(m); SigSpec outputs = module_outputs(m);
if (lut_attrs) { if (derive_luts) {
int no = 0; int no = 0;
for (auto bit : outputs) { for (auto bit : outputs) {
log_assert(bit.is_wire()); log_assert(bit.is_wire());

2
tests/select/mod-attribute.ys
View file

@ -41,7 +41,7 @@ module \top
end end
EOT EOT
cellmatch -lut_attrs * cellmatch -derive_luts *
select -set buffers a:lut=2'b10 %m select -set buffers a:lut=2'b10 %m
select -set inverters a:lut=2'b01 %m select -set inverters a:lut=2'b01 %m

8
tests/techmap/cellmatch.ys
View file

@ -77,3 +77,11 @@ opt_clean
equiv_induct equiv equiv_induct equiv
equiv_status -assert equiv_status -assert
design -reset
design -load gatelib
cellmatch -derive_luts
select -assert-any bufgate/w:Y a:lut=2'b10 %i
select -assert-any reducegate/w:X a:lut=8'b10000000 %i
select -assert-any reducegate/w:Y a:lut=8'b11111110 %i
select -assert-any fagate/w:X a:lut=8'b10010110 %i
select -assert-any fagate/w:Y a:lut=8'b11101000 %i