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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3

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This commit is contained in:
Clifford Wolf 2014-07-23 09:00:16 +02:00
parent c61467a32c
commit 260c19ec5a
4 changed files with 45 additions and 7 deletions
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2
passes/abc/abc.cc
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@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
clk_str = clk_str.substr(1);
}
if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1));
clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0));
}
if (dff_mode && clk_sig.size() == 0)

8
passes/sat/share.cc
View file

@ -292,8 +292,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
module->add(supercell);
RTLIL::SigSpec new_y1(y, y1.size());
RTLIL::SigSpec new_y2(y, y2.size());
RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size(), 0);
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@ -405,8 +405,8 @@ struct ShareWorker
supercell->connections["\\Y"] = y;
supercell->check();
RTLIL::SigSpec new_y1(y, y1.size());
RTLIL::SigSpec new_y2(y, y2.size());
RTLIL::SigSpec new_y1(y, y1.size(), 0);
RTLIL::SigSpec new_y2(y, y2.size(), 0);
module->connections.push_back(RTLIL::SigSig(y1, new_y1));
module->connections.push_back(RTLIL::SigSig(y2, new_y2));