mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 20:38:44 +00:00
Code Activity

fabulous: Add CLK to BRAM interface primitives

Browse source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-02-16 11:57:19 +01:00 committed by myrtle
parent a20804c6ed
commit 25e7cb3bbb
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
techlibs/fabulous/prims.v
View file

@ -93,13 +93,13 @@ module Global_Clock (output CLK);
endmodule
(* blackbox, keep *)
module InPass4_frame_config (output O0, O1, O2, O3);
module InPass4_frame_config (input CLK, output O0, O1, O2, O3);
endmodule
(* blackbox, keep *)
module OutPass4_frame_config (input I0, I1, I2, I3);
module OutPass4_frame_config (input CLK, I0, I1, I2, I3);
endmodule