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Major redesign of Verific SVA importer

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-02-27 20:33:15 +01:00
parent 6f26695d9b
commit 25e33d7ab8
2 changed files with 574 additions and 6 deletions
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2
tests/sva/sva_range.sv
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@ -5,7 +5,7 @@ module top (
default clocking @(posedge clk); endclocking
assert property (
a ##[*] b |=> c until ##[*] d
a ##[*] b |=> c until d
);
`ifndef FAIL