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VHDL only build support

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This commit is contained in:
Miodrag Milanovic 2024-06-07 14:58:33 +02:00
parent 54bf9ccf06
commit 25d50bb2af
3 changed files with 144 additions and 29 deletions
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6
frontends/verific/verificsva.cc
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@ -80,6 +80,7 @@ USING_YOSYS_NAMESPACE
using namespace Verific;
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
PRIVATE_NAMESPACE_BEGIN
// Non-deterministic FSM
@ -1878,5 +1879,8 @@ bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net)
worker.importer = importer;
return worker.net_to_ast_driver(net) != nullptr;
}
#else
YOSYS_NAMESPACE_BEGIN
pool<int> verific_sva_prims = {};
#endif
YOSYS_NAMESPACE_END