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rtlil: complicate extract again for packing

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This commit is contained in:
Emil J. Tywoniak 2026-04-23 17:47:17 +02:00
parent 14b0efeced
commit 25b9b796c4
5 changed files with 167 additions and 14 deletions
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71
tests/unit/kernel/rtlilHelpers.h Normal file
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@ -0,0 +1,71 @@
#ifndef RTLIL_HELPERS_H
#define RTLIL_HELPERS_H
#include <gtest/gtest.h>
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
class SigSpecRepTest : public ::testing::Test {
protected:
Design* d;
Module* m;
void SetUp() override {
d = new Design;
m = d->addModule("$test");
}
void TearDown() override {
delete d;
}
// Create n wires with given width
std::vector<Wire*> createWires(int count, int width = 4) {
std::vector<Wire*> wires;
for (int i = 0; i < count; i++) {
Wire* w = m->addWire(stringf("$w%d", i), width);
wires.push_back(w);
}
return wires;
}
// Append all wires to a SigSpec
SigSpec wiresAsSigSpec(const std::vector<Wire*>& wires) {
SigSpec sig;
for (auto w : wires)
sig.append(w);
return sig;
}
// Create a SigSpec of constants
SigSpec constsAsSigSpec(int count, int width = 4) {
SigSpec sig;
for (int i = 0; i < count; i++)
sig.append(Const(i, width));
return sig;
}
// Convert wires to pool of SigBits
pool<SigBit> wiresToPool(const std::vector<Wire*>& wires) {
pool<SigBit> pool;
for (auto w : wires)
for (auto &bit : SigSpec(w))
pool.insert(bit);
return pool;
}
// Convert wires to set of SigBits
std::set<SigBit> wiresToSet(const std::vector<Wire*>& wires) {
std::set<SigBit> set;
for (auto w : wires)
for (auto &bit : SigSpec(w))
set.insert(bit);
return set;
}
};
YOSYS_NAMESPACE_END
#endif /* RTLIL_HELPERS_H */

57
tests/unit/kernel/sigspecExtract2Test.cc Normal file
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@ -0,0 +1,57 @@
#include <gtest/gtest.h>
#include "kernel/rtlil.h"
#include "tests/unit/kernel/rtlilHelpers.h"
YOSYS_NAMESPACE_BEGIN
namespace RTLIL {
TEST_F(SigSpecRepTest, ExtractWires)
{
auto wires = createWires(4, 4);
SigSpec sig = wiresAsSigSpec(wires);
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
SigSpec extractedLast = sig.extract(12, 4);
EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
}
TEST_F(SigSpecRepTest, ExtractConsts)
{
{
SigSpec sig = constsAsSigSpec(4, 4);
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
SigSpec extractedLast = sig.extract(12, 4);
std::cout << log_signal(extractedFirst) << "\n";
EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
}
{
SigSpec sig;
sig.append(Const(0, 4));
sig.append(m->addWire("$foo", 4));
sig.append(Const(0, 4));
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
SigSpec extractedLast = sig.extract(8, 4);
EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
SigSpec extractedFirstTwo = sig.extract(0, 8);
EXPECT_EQ(extractedFirstTwo.rep_, SigSpec::Representation::BITS);
SigSpec extractedLastTwo = sig.extract(0, 8);
EXPECT_EQ(extractedLastTwo.rep_, SigSpec::Representation::BITS);
}
}
};
YOSYS_NAMESPACE_END

26
tests/unit/kernel/sigspecRemove2Test.cc
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@ -5,7 +5,7 @@
YOSYS_NAMESPACE_BEGIN
// Test fixture with helper functions
class SigSpecRemove2Test : public ::testing::Test {
class SigSpecRepTest : public ::testing::Test {
protected:
Design* d;
Module* m;
@ -64,7 +64,7 @@ protected:
}
};
TEST_F(SigSpecRemove2Test, WithSigSpecPattern)
TEST_F(SigSpecRepTest, WithSigSpecPattern)
{
auto wires = createWires(4);
SigSpec sig = wiresAsSigSpec(wires);
@ -84,7 +84,7 @@ TEST_F(SigSpecRemove2Test, WithSigSpecPattern)
EXPECT_EQ(sig, expected);
}
TEST_F(SigSpecRemove2Test, WithPoolPattern)
TEST_F(SigSpecRepTest, WithPoolPattern)
{
auto wires = createWires(3);
SigSpec sig = wiresAsSigSpec(wires);
@ -103,7 +103,7 @@ TEST_F(SigSpecRemove2Test, WithPoolPattern)
EXPECT_EQ(sig, expected);
}
TEST_F(SigSpecRemove2Test, WithSetPattern)
TEST_F(SigSpecRepTest, WithSetPattern)
{
auto wires = createWires(3);
SigSpec sig = wiresAsSigSpec(wires);
@ -122,7 +122,7 @@ TEST_F(SigSpecRemove2Test, WithSetPattern)
EXPECT_EQ(sig, expected);
}
TEST_F(SigSpecRemove2Test, ManyElements)
TEST_F(SigSpecRepTest, ManyElements)
{
const int num_wires = 100;
auto wires = createWires(num_wires);
@ -146,7 +146,7 @@ TEST_F(SigSpecRemove2Test, ManyElements)
}
// Test remove2 with very large dataset to check scaling
TEST_F(SigSpecRemove2Test, VeryLargeScalingTest)
TEST_F(SigSpecRepTest, VeryLargeScalingTest)
{
const int num_wires = 50000;
auto wires = createWires(num_wires);
@ -173,7 +173,7 @@ TEST_F(SigSpecRemove2Test, VeryLargeScalingTest)
}
// Test multiple sequential removals (simulates removeSignalFromCaseTree)
TEST_F(SigSpecRemove2Test, MultipleSequentialRemovals)
TEST_F(SigSpecRepTest, MultipleSequentialRemovals)
{
const int num_wires = 512;
auto wires = createWires(num_wires);
@ -204,7 +204,7 @@ TEST_F(SigSpecRemove2Test, MultipleSequentialRemovals)
}
// Test remove2 with very large dataset to check scaling
TEST_F(SigSpecRemove2Test, PoolOverloadLargeDataset)
TEST_F(SigSpecRepTest, PoolOverloadLargeDataset)
{
const int num_wires = 50000;
auto wires = createWires(num_wires, 1);
@ -228,7 +228,7 @@ TEST_F(SigSpecRemove2Test, PoolOverloadLargeDataset)
}
// Test set overload (same perf characteristics as pool)
TEST_F(SigSpecRemove2Test, SetOverloadLargeDataset)
TEST_F(SigSpecRepTest, SetOverloadLargeDataset)
{
const int num_wires = 50000;
auto wires = createWires(num_wires, 1);
@ -252,7 +252,7 @@ TEST_F(SigSpecRemove2Test, SetOverloadLargeDataset)
}
// Worst case: remove almost all elements
TEST_F(SigSpecRemove2Test, RemoveAlmostAllElements)
TEST_F(SigSpecRepTest, RemoveAlmostAllElements)
{
const int num_wires = 10000;
auto wires = createWires(num_wires, 1);
@ -269,7 +269,7 @@ TEST_F(SigSpecRemove2Test, RemoveAlmostAllElements)
EXPECT_EQ(sig[0].wire, wires[num_wires - 1]);
}
TEST_F(SigSpecRemove2Test, EmptyPattern)
TEST_F(SigSpecRepTest, EmptyPattern)
{
auto wires = createWires(1);
SigSpec sig(wires[0]);
@ -285,7 +285,7 @@ TEST_F(SigSpecRemove2Test, EmptyPattern)
}
// Test that NULL wire bits (constants) are not removed
TEST_F(SigSpecRemove2Test, NullWireBitsStay)
TEST_F(SigSpecRepTest, NullWireBitsStay)
{
auto wires = createWires(1);
SigSpec sig;
@ -309,7 +309,7 @@ TEST_F(SigSpecRemove2Test, NullWireBitsStay)
EXPECT_EQ(sig, expected);
}
TEST_F(SigSpecRemove2Test, PartialBitRemoval)
TEST_F(SigSpecRepTest, PartialBitRemoval)
{
Wire* w = m->addWire("$w1", 8);
SigSpec sig(w);