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rtlil: complicate extract again for packing

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This commit is contained in:
Emil J. Tywoniak 2026-04-23 17:47:17 +02:00
parent 14b0efeced
commit 25b9b796c4
5 changed files with 167 additions and 14 deletions
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24
kernel/rtlil.cc
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@ -5273,9 +5273,31 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
log_assert(offset + length <= size());
std::vector<SigBit> extracted;
SigBit first;
bool is_packing = true;
for (int i = offset; i < offset + length; i++) {
extracted.push_back((*this)[i]);
bool was_packing_before = is_packing;
SigBit bit = (*this)[i];
if (i == offset) {
first = bit;
if (!bit.wire)
is_packing = false;
} else {
if (bit.wire != first.wire)
is_packing = false;
if (bit.wire)
if (bit.offset != first.offset + (i - offset))
is_packing = false;
}
if (was_packing_before && !is_packing)
for (int j = offset; j < i; j++)
extracted.push_back((*this)[j]);
if (!is_packing)
extracted.push_back((*this)[i]);
}
if (is_packing)
return SigChunk(first.wire, first.offset, length);
return extracted;
}

3
kernel/rtlil.h
View file

@ -1400,6 +1400,9 @@ struct RTLIL::SigSpecConstIterator
struct RTLIL::SigSpec
{
private:
friend class SigSpecRepTest;
FRIEND_TEST(SigSpecRepTest, ExtractWires);
FRIEND_TEST(SigSpecRepTest, ExtractConsts);
enum Representation : char {
CHUNK,
BITS,