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Set port_id for Verific PortBus wires

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Robert O'Callahan 2025-10-23 20:46:11 +00:00
parent 37875fdedf
commit 25aafab86b
2 changed files with 14 additions and 0 deletions
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13
tests/verific/port_bus_order.ys Normal file
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verific -sv <<EOT
module simple (
input [3:0] I2,
input [3:0] I1,
output [3:0] result
);
assign result = I2 & I1;
endmodule
EOT
verific -import simple
write_verilog verilog_port_bus_order.out
!grep -qF 'simple(I2, I1, result)' verilog_port_bus_order.out