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Oh deary me

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Eddie Hung 2019-12-04 20:33:24 -08:00
parent c8a7bc5d3a
commit 258a34e6f1
1 changed files with 4 additions and 4 deletions
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8
techlibs/xilinx/cells_sim.v
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@ -378,10 +378,10 @@ module FDPE (
parameter [0:0] IS_PRE_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ; 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ; 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= Q ; 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= Q ; 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase endgenerate endcase endgenerate
endmodule endmodule