From 2585636d18a4ac9c730a819f732bc9f05b880793 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Sun, 2 Jun 2024 22:24:29 -0700 Subject: [PATCH] Use ability to get/set IMPORT runtime flags --- frontends/verific/verific.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 63281949f..405cf3ff8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1195,7 +1195,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX) { - // SILIMATE: WARN FOR THIS CASE BECAUSE + // SILIMATE: WARN FOR THIS CASE BECAUSE YOSYS CAN DO WHATEVER IT WANTS log_warning("Using OPER_WIDE_CASE_SELECT_BOX! This could result in long chains of logic...\n"); RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value"); @@ -3248,6 +3248,7 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("db_allow_external_nets", 1); RuntimeFlags::SetVar("db_infer_wide_operators", 1); + // RuntimeFlags::SetVar("db_infer_wide_operators_post_elaboration", 0); // SILIMATE: add to improve optimization (QoR) RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); // Properly respect order of read and write for rams @@ -3257,7 +3258,7 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); RuntimeFlags::SetVar("veri_break_loops", 0); // SILIMATE: add to avoid breaking loops - RuntimeFlags::SetVar("veri_optimize_wide_selector", 1); // SILIMATE: add to optimize wide selector (FIXME: check if this is ok) + // RuntimeFlags::SetVar("veri_optimize_wide_selector", 1); // SILIMATE: add to optimize wide selector (FIXME: check if this is ok) RuntimeFlags::SetVar("veri_ignore_assertion_statements", 1); // SILIMATE: add to ignore SVA/asserts #ifdef VERIFIC_VHDL_SUPPORT