mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Fixed "abc" pass for clk and enable signals driven by logic

Browse source
This commit is contained in:
Clifford Wolf 2014-12-21 11:13:25 +01:00
parent f7b323196f
commit 25844b5683
1 changed files with 8 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

14
passes/abc/abc.cc
View file

@ -147,6 +147,8 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
if (GetSize(en_sig) != 0)
return;
goto matching_dff;
}
@ -692,12 +694,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
}
}
if (clk_sig.size() != 0)
mark_port(clk_sig);
if (en_sig.size() != 0)
mark_port(en_sig);
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells_.size());
for (auto &it : module->cells_)
@ -715,6 +711,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
for (auto &port_it : cell_it.second->connections())
mark_port(port_it.second);
if (clk_sig.size() != 0)
mark_port(clk_sig);
if (en_sig.size() != 0)
mark_port(en_sig);
handle_loops();
std::string buffer = stringf("%s/input.blif", tempdir_name.c_str());