3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-12 20:18:20 +00:00

Fixed const2big performance bug

This commit is contained in:
Clifford Wolf 2015-04-09 13:20:19 +02:00
parent be7b9b34ca
commit 25781e329b

View file

@ -41,21 +41,28 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos) static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
{ {
BigInteger result = 0, this_bit = 1; BigUnsigned mag;
for (size_t i = 0; i < val.bits.size(); i++) {
if (val.bits[i] == RTLIL::State::S1) { BigInteger::Sign sign = BigInteger::positive;
if (as_signed && i+1 == val.bits.size()) State inv_sign_bit = RTLIL::State::S1;
result -= this_bit; size_t num_bits = val.bits.size();
else
result += this_bit; if (as_signed && num_bits && val.bits[num_bits-1] == RTLIL::State::S1) {
} inv_sign_bit = RTLIL::State::S0;
else if (val.bits[i] != RTLIL::State::S0) { sign = BigInteger::negative;
if (undef_bit_pos < 0) num_bits--;
undef_bit_pos = i;
}
this_bit *= 2;
} }
return result;
for (size_t i = 0; i < num_bits; i++)
if (val.bits[i] == RTLIL::State::S0 || val.bits[i] == RTLIL::State::S1)
mag.setBit(i, val.bits[i] == inv_sign_bit);
else if (undef_bit_pos < 0)
undef_bit_pos = i;
if (sign == BigInteger::negative)
mag += 1;
return BigInteger(mag, sign);
} }
static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos) static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos)