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https://github.com/YosysHQ/yosys
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splitnets
This commit is contained in:
Alain Dargelas
parent
ecd2ac4302
commit
25553a8ca9
1 changed files with 147 additions and 40 deletions
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@ -64,7 +64,19 @@ void lhs2rhs_rhs2lhs(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
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}
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}
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void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout, RTLIL::Cell *cell, int fanout,
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RTLIL::Wire* getParentWire(const RTLIL::SigSpec& sigspec) {
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if (sigspec.empty()) {
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return nullptr; // Empty SigSpec, no parent wire
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}
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// Get the first SigBit
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const RTLIL::SigBit& first_bit = sigspec[0];
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// Return the parent wire
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return first_bit.wire;
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}
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void fixfanout(RTLIL::Design* design, RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout, RTLIL::Cell *cell, int fanout,
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int limit)
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{
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if (fanout <= limit) {
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@ -82,9 +94,9 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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std::cout << "limit: " << limit << "\n";
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std::cout << "num_buffers: " << num_buffers << "\n";
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std::cout << "max_output_per_buffer: " << max_output_per_buffer << "\n";
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std::vector<RTLIL::SigSpec> buffer_outputs;
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std::vector<RTLIL::Cell *> buffers;
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std::cout << "CELL: " << cell->name.c_str() << "\n" << std::flush;
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// Get cell output
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RTLIL::SigSpec cellOutSig;
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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@ -94,61 +106,102 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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break;
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}
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}
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// Create buffers and new wires
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std::vector<std::vector<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>>> buffer_outputs;
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std::vector<std::vector<RTLIL::Cell *>> buffers;
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for (int i = 0; i < num_buffers; ++i) {
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RTLIL::Cell *buffer = module->addCell(NEW_ID2_SUFFIX("fbuf"), ID($buf)); // Assuming BUF is defined
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RTLIL::SigSpec buffer_output = module->addWire(NEW_ID2_SUFFIX("fbuf"));
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buffer->setPort(ID(A), cellOutSig);
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buffer->setPort(ID(Y), sigmap(buffer_output));
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buffer_outputs.push_back(buffer_output);
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buffers.push_back(buffer);
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std::vector<std::pair<RTLIL::SigSpec, RTLIL::SigSpec>> buffer_chunk_outputs;
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std::vector<RTLIL::Cell *> buffer_chunks;
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for (SigChunk chunk : cellOutSig.chunks()) {
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RTLIL::Cell *buffer = module->addCell(NEW_ID2_SUFFIX("fbuf"), ID($pos));
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RTLIL::SigSpec buffer_output = module->addWire(NEW_ID2_SUFFIX("fbuf"), chunk.size());
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buffer->setPort(ID(A), chunk);
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buffer->setPort(ID(Y), sigmap(buffer_output));
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buffer->fixup_parameters();
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buffer_chunk_outputs.push_back(std::make_pair(chunk, buffer_output)); // Old - New
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buffer_chunks.push_back(buffer);
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}
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buffer_outputs.push_back(buffer_chunk_outputs);
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buffers.push_back(buffer_chunks);
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}
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// Cumulate all cells in the fanout of this cell
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std::set<Cell *> cells = sig2CellsInFanout[cellOutSig];
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for (int i = 0 ; i < cellOutSig.size(); i++) {
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SigSpec bit_sig = cellOutSig.extract(i, 1);
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for (Cell* c : sig2CellsInFanout[sigmap(bit_sig)]) {
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cells.insert(c);
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}
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}
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int indexCurrentBuffer = 0;
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int indexFanout = 0;
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std::map<Cell *, int> bufferActualFanout;
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for (Cell *c : cells) {
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std::cout << " CELL in fanout: " << c->name.c_str() << "\n" << std::flush;
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for (auto &conn : c->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (c->input(portName)) {
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if (actual.is_chunk()) {
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if (sigmap(actual) == cellOutSig) {
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std::cout << "vector size: " << buffer_outputs.size() << std::endl;
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std::cout << "index : " << indexCurrentBuffer << std::endl;
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c->setPort(portName, buffer_outputs[indexCurrentBuffer]);
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sig2CellsInFanout[sigmap(buffer_outputs[indexCurrentBuffer])].insert(c);
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indexFanout++;
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bufferActualFanout[buffers[indexCurrentBuffer]] = indexFanout;
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if (indexFanout >= max_output_per_buffer) {
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indexFanout = 0;
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indexCurrentBuffer++;
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std::cout << " CHUNK, indexCurrentBuffer: " << indexCurrentBuffer << " buffer_outputs " << buffer_outputs.size() << std::endl;
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for (std::pair<RTLIL::SigSpec, RTLIL::SigSpec>& old_new : buffer_outputs[indexCurrentBuffer]) {
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if (sigmap(old_new.first) == sigmap(actual)) {
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std::cout << " MATCH" << std::endl;
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c->setPort(portName, old_new.second);
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sig2CellsInFanout[sigmap(old_new.second)].insert(c);
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indexFanout++;
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for (Cell* c : buffers[indexCurrentBuffer]) {
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bufferActualFanout[c] = indexFanout;
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}
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break;
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}
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break;
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}
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if (indexFanout >= max_output_per_buffer) {
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indexFanout = 0;
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if (buffer_outputs.size()-1 > indexCurrentBuffer)
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indexCurrentBuffer++;
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}
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} else {
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std::cout << "NOT CHUNK" << std::endl;
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bool match = false;
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for (SigChunk chunk : actual.chunks()) {
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if (sigmap(SigSpec(chunk)) == cellOutSig) {
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match = true;
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break;
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for (SigChunk chunka : actual.chunks()) {
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for (SigChunk chunks : cellOutSig.chunks()) {
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if (sigmap(SigSpec(chunka)) == SigSpec(chunks)) {
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match = true;
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break;
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}
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}
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if (match)
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break;
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}
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if (match) {
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std::cout << "MATCH" << std::endl;
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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if (sigmap(SigSpec(chunk)) == cellOutSig) {
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newChunks.push_back(buffer_outputs[indexCurrentBuffer].as_wire());
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} else {
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bool replaced = false;
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for (std::pair<RTLIL::SigSpec, RTLIL::SigSpec>& old_new : buffer_outputs[indexCurrentBuffer]) {
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if (sigmap(old_new.first) == sigmap(SigSpec(chunk))) {
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newChunks.push_back(old_new.second.as_chunk());
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sig2CellsInFanout[sigmap(old_new.second)].insert(c);
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replaced = true;
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break;
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}
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}
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if (!replaced) {
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newChunks.push_back(chunk);
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}
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}
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c->setPort(portName, newChunks);
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sig2CellsInFanout[sigmap(buffer_outputs[indexCurrentBuffer])].insert(c);
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indexFanout++;
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bufferActualFanout[buffers[indexCurrentBuffer]] = indexFanout;
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for (Cell *c : buffers[indexCurrentBuffer]) {
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bufferActualFanout[c] = indexFanout;
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}
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if (indexFanout >= max_output_per_buffer) {
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indexFanout = 0;
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indexCurrentBuffer++;
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if (buffer_outputs.size()-1 > indexCurrentBuffer)
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indexCurrentBuffer++;
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}
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break;
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}
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@ -160,25 +213,42 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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// Recursively fix the fanout of the newly created buffers
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for (std::map<Cell *, int>::iterator itr = bufferActualFanout.begin(); itr != bufferActualFanout.end(); itr++) {
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if (itr->second == 1) {
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std::cout << "Buffer with fanout 1: " << itr->first->name.c_str() << std::endl;
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RTLIL::SigSpec bufferInSig = itr->first->getPort(ID::A);
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RTLIL::SigSpec bufferOutSig = itr->first->getPort(ID::Y);
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//std::cout << "bufferOutSig: " << bufferOutSig.as_wire()->name.c_str()
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// << " bufferInSig: " << bufferInSig.as_wire()->name.c_str() << std::endl;
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// Remove newly created buffers with a fanout of 1
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std::cout << "Buffer of 1" << std::endl;
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for (Cell *c : cells) {
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std::cout << "Cell in its fanout: " << c->name.c_str() << std::endl;
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for (auto &conn : c->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (c->input(portName)) {
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if (sigmap(buffer_outputs[indexCurrentBuffer]) == sigmap(actual)) {
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c->setPort(portName, cellOutSig);
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std::cout << "Remove buffer of 1" << std::endl;
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module->remove(buffers[indexCurrentBuffer]);
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// module->remove({buffer_outputs[indexCurrentBuffer].as_wire()});
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break;
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if (actual.is_chunk()) {
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if (bufferOutSig == sigmap(actual)) {
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std::cout << "Replace1: " << getParentWire(bufferOutSig)->name.c_str() << " by " << getParentWire(bufferInSig)->name.c_str() << std::endl;
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c->setPort(portName, bufferInSig);
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}
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} else {
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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if (sigmap(SigSpec(chunk)) == sigmap(bufferOutSig)) {
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std::cout << "Replace2: " << getParentWire(bufferOutSig)->name.c_str() << " by " << getParentWire(bufferInSig)->name.c_str() << std::endl;
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newChunks.push_back(bufferInSig.as_chunk());
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} else {
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newChunks.push_back(chunk);
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}
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}
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c->setPort(portName, newChunks);
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}
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}
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}
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}
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module->remove(itr->first);
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module->remove({bufferOutSig.as_wire()});
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} else {
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fixfanout(module, sigmap, sig2CellsInFanout, itr->first, itr->second, limit);
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fixfanout(design, module, sigmap, sig2CellsInFanout, itr->first, itr->second, limit);
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}
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}
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}
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@ -270,23 +340,59 @@ struct AnnotateCellFanout : public ScriptPass {
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for (auto module : design->selected_modules()) {
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bool fixedFanout = false;
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{
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// Split output nets of cells with high fanout
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SigMap sigmap(module);
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dict<Cell *, int> cellFanout;
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dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanout;
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calculateFanout(module, sigmap, sig2CellsInFanout, cellFanout);
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// Add attribute with fanout info to every cell
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std::vector<Cell*> cellsToFixFanout;
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for (auto itrCell : cellFanout) {
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Cell *cell = itrCell.first;
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int fanout = itrCell.second;
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if (limit > 0 && (fanout > limit)) {
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fixfanout(module, sigmap, sig2CellsInFanout, cell, fanout, limit);
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cellsToFixFanout.push_back(cell);
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}
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}
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std::string netsToSplit;
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for (Cell* cell : cellsToFixFanout) {
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RTLIL::SigSpec cellOutSig;
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (cell->output(portName)) {
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cellOutSig = sigmap(actual);
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break;
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}
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}
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netsToSplit += std::string(" w:") + getParentWire(cellOutSig)->name.c_str();
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}
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std::string splitnets = std::string("splitnets ") + netsToSplit;
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Pass::call(design, splitnets);
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}
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{
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// Fix high fanout
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SigMap sigmap(module);
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dict<Cell *, int> cellFanout;
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dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanout;
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calculateFanout(module, sigmap, sig2CellsInFanout, cellFanout);
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for (auto itrCell : cellFanout) {
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Cell *cell = itrCell.first;
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int fanout = itrCell.second;
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if (limit > 0 && (fanout > limit)) {
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fixfanout(design, module, sigmap, sig2CellsInFanout, cell, fanout, limit);
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fixedFanout = true;
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} else {
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// Add attribute with fanout info to every cell
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cell->set_string_attribute("$FANOUT", std::to_string(fanout));
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}
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}
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}
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if (fixedFanout) {
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// If Fanout got fixed, recalculate and annotate final fanout
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SigMap sigmap(module);
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dict<Cell *, int> cellFanout;
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dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanout;
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@ -294,6 +400,7 @@ struct AnnotateCellFanout : public ScriptPass {
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for (auto itrCell : cellFanout) {
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Cell *cell = itrCell.first;
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int fanout = itrCell.second;
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// Add attribute with fanout info to every cell
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cell->set_string_attribute("$FANOUT", std::to_string(fanout));
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}
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}
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