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https://github.com/YosysHQ/yosys
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Merge branch 'eddie/abc9_refactor' into xaig_dff
This commit is contained in:
commit
24c934f1af
171 changed files with 6745 additions and 4523 deletions
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@ -195,7 +195,7 @@ struct SynthXilinxPass : public ScriptPass
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continue;
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}
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if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
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widemux = std::stoi(args[++argidx]);
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widemux = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-abc9") {
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@ -236,8 +236,13 @@ struct SynthXilinxPass : public ScriptPass
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run("read_verilog -lib +/xilinx/cells_xtra.v");
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if (!nobram || help_mode)
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run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
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if (help_mode) {
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run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
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} else if (family == "xc6s") {
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run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
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} else if (family == "xc7") {
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run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
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}
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run(stringf("hierarchy -check %s", top_opt.c_str()));
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}
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@ -280,9 +285,19 @@ struct SynthXilinxPass : public ScriptPass
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}
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if (check_label("bram", "(skip if '-nobram')")) {
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if (!nobram || help_mode) {
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run("memory_bram -rules +/xilinx/brams.txt");
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run("techmap -map +/xilinx/brams_map.v");
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if (help_mode) {
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run("memory_bram -rules +/xilinx/{family}_brams.txt");
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run("techmap -map +/xilinx/{family}_brams_map.v");
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} else if (!nobram) {
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if (family == "xc6s") {
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run("memory_bram -rules +/xilinx/xc6s_brams.txt");
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run("techmap -map +/xilinx/xc6s_brams_map.v");
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} else if (family == "xc7") {
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run("memory_bram -rules +/xilinx/xc7_brams.txt");
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run("techmap -map +/xilinx/xc7_brams_map.v");
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} else {
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log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
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}
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}
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}
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