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Update frontends to avoid bits()

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This commit is contained in:
Robert O'Callahan 2025-08-28 01:55:26 +00:00
parent c89a4da607
commit 24a95bd6cf
6 changed files with 37 additions and 26 deletions
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2
frontends/aiger/aigerparse.cc
View file

@ -448,7 +448,7 @@ void AigerReader::parse_xaiger()
bool success = ce.eval(o); bool success = ce.eval(o);
log_assert(success); log_assert(success);
log_assert(o.wire == nullptr); log_assert(o.wire == nullptr);
lut_mask.bits()[gray] = o.data; lut_mask.set(gray, o.data);
} }
RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)); RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID));
log_assert(output_cell); log_assert(output_cell);

4
frontends/ast/ast.cc
View file

@ -1076,8 +1076,10 @@ RTLIL::Const AstNode::realAsConst(int width)
bool is_negative = v < 0; bool is_negative = v < 0;
if (is_negative) if (is_negative)
v *= -1; v *= -1;
RTLIL::Const::Builder b(width);
for (int i = 0; i < width; i++, v /= 2) for (int i = 0; i < width; i++, v /= 2)
result.bits().push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0); b.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
result = b.build();
if (is_negative) if (is_negative)
result = const_neg(result, result, false, false, result.size()); result = const_neg(result, result, false, false, result.size());
} }

16
frontends/ast/genrtlil.cc
View file

@ -732,16 +732,17 @@ struct AST_INTERNAL::ProcessGenerator
current_case->actions.push_back(SigSig(en, true)); current_case->actions.push_back(SigSig(en, true));
RTLIL::SigSpec triggers; RTLIL::SigSpec triggers;
RTLIL::Const polarity; RTLIL::Const::Builder polarity_builder;
for (auto sync : proc->syncs) { for (auto sync : proc->syncs) {
if (sync->type == RTLIL::STp) { if (sync->type == RTLIL::STp) {
triggers.append(sync->signal); triggers.append(sync->signal);
polarity.bits().push_back(RTLIL::S1); polarity_builder.push_back(RTLIL::S1);
} else if (sync->type == RTLIL::STn) { } else if (sync->type == RTLIL::STn) {
triggers.append(sync->signal); triggers.append(sync->signal);
polarity.bits().push_back(RTLIL::S0); polarity_builder.push_back(RTLIL::S0);
} }
} }
RTLIL::Const polarity = polarity_builder.build();
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print)); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print));
set_src_attr(cell, ast); set_src_attr(cell, ast);
@ -829,16 +830,17 @@ struct AST_INTERNAL::ProcessGenerator
current_case->actions.push_back(SigSig(en, true)); current_case->actions.push_back(SigSig(en, true));
RTLIL::SigSpec triggers; RTLIL::SigSpec triggers;
RTLIL::Const polarity; RTLIL::Const::Builder polarity_builder;
for (auto sync : proc->syncs) { for (auto sync : proc->syncs) {
if (sync->type == RTLIL::STp) { if (sync->type == RTLIL::STp) {
triggers.append(sync->signal); triggers.append(sync->signal);
polarity.bits().push_back(RTLIL::S1); polarity_builder.push_back(RTLIL::S1);
} else if (sync->type == RTLIL::STn) { } else if (sync->type == RTLIL::STn) {
triggers.append(sync->signal); triggers.append(sync->signal);
polarity.bits().push_back(RTLIL::S0); polarity_builder.push_back(RTLIL::S0);
} }
} }
RTLIL::Const polarity = polarity_builder.build();
RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
set_src_attr(cell, ast); set_src_attr(cell, ast);
@ -893,7 +895,7 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx); RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
for (int i = 0; i < portid; i++) { for (int i = 0; i < portid; i++) {
int new_bit = port_map[std::make_pair(memid, i)]; int new_bit = port_map[std::make_pair(memid, i)];
priority_mask.bits()[new_bit] = orig_priority_mask[i]; priority_mask.set(new_bit, orig_priority_mask[i]);
} }
action.priority_mask = priority_mask; action.priority_mask = priority_mask;
sync->mem_write_actions.push_back(action); sync->mem_write_actions.push_back(action);

11
frontends/ast/simplify.cc
View file

@ -4366,7 +4366,7 @@ replace_fcall_later:;
log_assert(a.size() == b.size()); log_assert(a.size() == b.size());
for (auto i = 0; i < a.size(); i++) for (auto i = 0; i < a.size(); i++)
if (a[i] != b[i]) if (a[i] != b[i])
a.bits()[i] = RTLIL::State::Sx; a.set(i, RTLIL::State::Sx);
newNode = mkconst_bits(location, a.to_bits(), sign_hint); newNode = mkconst_bits(location, a.to_bits(), sign_hint);
} else if (children[1]->isConst() && children[2]->isConst()) { } else if (children[1]->isConst() && children[2]->isConst()) {
newNode = std::make_unique<AstNode>(location, AST_REALVALUE); newNode = std::make_unique<AstNode>(location, AST_REALVALUE);
@ -5368,8 +5368,11 @@ bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
offset -= variables.at(str).offset; offset -= variables.at(str).offset;
if (variables.at(str).range_swapped) if (variables.at(str).range_swapped)
offset = -offset; offset = -offset;
std::vector<RTLIL::State> &var_bits = variables.at(str).val.bits(); const RTLIL::Const &val = variables.at(str).val;
std::vector<RTLIL::State> new_bits(var_bits.begin() + offset, var_bits.begin() + offset + width); std::vector<RTLIL::State> new_bits;
new_bits.reserve(width);
for (int i = 0; i < width; i++)
new_bits.push_back(val[offset+i]);
auto newNode = mkconst_bits(location, new_bits, variables.at(str).is_signed); auto newNode = mkconst_bits(location, new_bits, variables.at(str).is_signed);
newNode->cloneInto(*this); newNode->cloneInto(*this);
return true; return true;
@ -5513,7 +5516,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
int index = i + offset - v.offset; int index = i + offset - v.offset;
if (v.range_swapped) if (v.range_swapped)
index = -index; index = -index;
v.val.bits().at(index) = r.at(i); v.val.set(index, r.at(i));
} }
} }

23
frontends/blif/blifparse.cc
View file

@ -149,7 +149,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (buffer[0] == '.') if (buffer[0] == '.')
{ {
if (lutptr) { if (lutptr) {
for (auto &bit : lutptr->bits()) for (auto bit : *lutptr)
if (bit == RTLIL::State::Sx) if (bit == RTLIL::State::Sx)
bit = lut_default_state; bit = lut_default_state;
lutptr = NULL; lutptr = NULL;
@ -321,9 +321,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
const_v = Const(str); const_v = Const(str);
} else { } else {
int n = strlen(v); int n = strlen(v);
const_v.bits().resize(n); Const::Builder const_v_builder(n);
for (int i = 0; i < n; i++) for (int i = 0; i < n; i++)
const_v.bits()[i] = v[n-i-1] != '0' ? State::S1 : State::S0; const_v_builder.push_back(v[n-i-1] != '0' ? State::S1 : State::S0);
const_v = const_v_builder.build();
} }
if (!strcmp(cmd, ".attr")) { if (!strcmp(cmd, ".attr")) {
if (obj_attributes == nullptr) { if (obj_attributes == nullptr) {
@ -563,21 +564,23 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len); log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len);
sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1; sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1;
Const::Builder table_bits_builder(input_len * 2);
for (int i = 0; i < input_len; i++) for (int i = 0; i < input_len; i++)
switch (input[i]) { switch (input[i]) {
case '0': case '0':
sopcell->parameters[ID::TABLE].bits().push_back(State::S1); table_bits_builder.push_back(State::S1);
sopcell->parameters[ID::TABLE].bits().push_back(State::S0); table_bits_builder.push_back(State::S0);
break; break;
case '1': case '1':
sopcell->parameters[ID::TABLE].bits().push_back(State::S0); table_bits_builder.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits().push_back(State::S1); table_bits_builder.push_back(State::S1);
break; break;
default: default:
sopcell->parameters[ID::TABLE].bits().push_back(State::S0); table_bits_builder.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits().push_back(State::S0); table_bits_builder.push_back(State::S0);
break; break;
} }
sopcell->parameters[ID::TABLE].append(table_bits_builder.build());
if (sopmode == -1) { if (sopmode == -1) {
sopmode = (*output == '1'); sopmode = (*output == '1');
@ -605,7 +608,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto try_next_value; goto try_next_value;
} }
} }
lutptr->bits().at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1; lutptr->set(i, !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1);
try_next_value:; try_next_value:;
} }

7
frontends/rtlil/rtlil_parser.y
View file

@ -455,9 +455,10 @@ constant:
} }
while ((int)bits.size() > width) while ((int)bits.size() > width)
bits.pop_back(); bits.pop_back();
$$ = new RTLIL::Const; RTLIL::Const::Builder builder(bits.size());
for (auto it = bits.begin(); it != bits.end(); it++) for (RTLIL::State bit : bits)
$$->bits().push_back(*it); builder.push_back(bit);
$$ = new RTLIL::Const(builder.build());
if (is_signed) { if (is_signed) {
$$->flags |= RTLIL::CONST_FLAG_SIGNED; $$->flags |= RTLIL::CONST_FLAG_SIGNED;
} }