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Update frontends to avoid bits()
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parent
c89a4da607
commit
24a95bd6cf
6 changed files with 37 additions and 26 deletions
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@ -732,16 +732,17 @@ struct AST_INTERNAL::ProcessGenerator
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current_case->actions.push_back(SigSig(en, true));
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RTLIL::SigSpec triggers;
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RTLIL::Const polarity;
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RTLIL::Const::Builder polarity_builder;
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for (auto sync : proc->syncs) {
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if (sync->type == RTLIL::STp) {
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triggers.append(sync->signal);
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polarity.bits().push_back(RTLIL::S1);
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polarity_builder.push_back(RTLIL::S1);
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} else if (sync->type == RTLIL::STn) {
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triggers.append(sync->signal);
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polarity.bits().push_back(RTLIL::S0);
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polarity_builder.push_back(RTLIL::S0);
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}
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}
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RTLIL::Const polarity = polarity_builder.build();
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print));
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set_src_attr(cell, ast);
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@ -829,16 +830,17 @@ struct AST_INTERNAL::ProcessGenerator
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current_case->actions.push_back(SigSig(en, true));
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RTLIL::SigSpec triggers;
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RTLIL::Const polarity;
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RTLIL::Const::Builder polarity_builder;
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for (auto sync : proc->syncs) {
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if (sync->type == RTLIL::STp) {
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triggers.append(sync->signal);
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polarity.bits().push_back(RTLIL::S1);
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polarity_builder.push_back(RTLIL::S1);
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} else if (sync->type == RTLIL::STn) {
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triggers.append(sync->signal);
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polarity.bits().push_back(RTLIL::S0);
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polarity_builder.push_back(RTLIL::S0);
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}
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}
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RTLIL::Const polarity = polarity_builder.build();
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RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
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set_src_attr(cell, ast);
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@ -893,7 +895,7 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx);
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for (int i = 0; i < portid; i++) {
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int new_bit = port_map[std::make_pair(memid, i)];
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priority_mask.bits()[new_bit] = orig_priority_mask[i];
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priority_mask.set(new_bit, orig_priority_mask[i]);
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}
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action.priority_mask = priority_mask;
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sync->mem_write_actions.push_back(action);
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