mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
Major rewrite of "freduce" command
This commit is contained in:
Clifford Wolf
parent
e501b8e5c7
commit
249ef8695a
4 changed files with 373 additions and 321 deletions
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@ -35,21 +35,19 @@ typedef ezSAT ezDefaultSAT;
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struct SatGen
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{
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ezSAT *ez;
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RTLIL::Design *design;
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SigMap *sigmap;
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std::string prefix;
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SigPool initial_state;
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bool ignore_div_by_zero;
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bool model_undef;
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SatGen(ezSAT *ez, RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string()) :
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ez(ez), design(design), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)
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SatGen(ezSAT *ez, SigMap *sigmap, std::string prefix = std::string()) :
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ez(ez), sigmap(sigmap), prefix(prefix), ignore_div_by_zero(false), model_undef(false)
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{
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}
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void setContext(RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string())
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void setContext(SigMap *sigmap, std::string prefix = std::string())
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{
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this->design = design;
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this->sigmap = sigmap;
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this->prefix = prefix;
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}
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@ -148,7 +148,7 @@ struct VlogHammerReporter
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ezDefaultSAT ez;
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SigMap sigmap(module);
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SatGen satgen(&ez, design, &sigmap);
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SatGen satgen(&ez, &sigmap);
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satgen.model_undef = model_undef;
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for (auto &c : module->cells)
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@ -28,337 +28,386 @@
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#include <string.h>
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#include <algorithm>
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#define NUM_INITIAL_RANDOM_TEST_VECTORS 10
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namespace {
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bool noinv_mode;
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int verbose_level;
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typedef std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>>> drivers_t;
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struct equiv_bit_t
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{
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int depth;
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bool inverted;
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RTLIL::SigBit bit;
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bool operator<(const equiv_bit_t &other) const {
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if (depth != other.depth)
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return depth < other.depth;
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if (inverted != other.inverted)
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return inverted < other.inverted;
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return bit < other.bit;
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}
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};
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struct FindReducedInputs
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{
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SigMap &sigmap;
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drivers_t &drivers;
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ezDefaultSAT ez;
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std::set<RTLIL::Cell*> ez_cells;
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SatGen satgen;
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FindReducedInputs(SigMap &sigmap, drivers_t &drivers) :
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sigmap(sigmap), drivers(drivers), satgen(&ez, &sigmap)
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{
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satgen.model_undef = true;
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}
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void register_cone_worker(std::set<RTLIL::SigBit> &pi, std::set<RTLIL::SigBit> &sigdone, RTLIL::SigBit out)
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{
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if (out.wire == NULL)
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return;
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if (sigdone.count(out) != 0)
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return;
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sigdone.insert(out);
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if (drivers.count(out) != 0) {
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std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
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if (ez_cells.count(drv.first) == 0) {
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satgen.setContext(&sigmap, "A");
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if (!satgen.importCell(drv.first))
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log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
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satgen.setContext(&sigmap, "B");
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if (!satgen.importCell(drv.first))
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log_abort();
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ez_cells.insert(drv.first);
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}
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for (auto &bit : drv.second)
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register_cone_worker(pi, sigdone, bit);
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} else
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pi.insert(out);
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}
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void register_cone(std::vector<RTLIL::SigBit> &pi, RTLIL::SigBit out)
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{
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std::set<RTLIL::SigBit> pi_set, sigdone;
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register_cone_worker(pi_set, sigdone, out);
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pi.clear();
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pi.insert(pi.end(), pi_set.begin(), pi_set.end());
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}
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void analyze(std::vector<RTLIL::SigBit> &reduced_inputs, RTLIL::SigBit output)
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{
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if (verbose_level >= 1)
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log(" Analyzing input cone for signal %s:\n", log_signal(output));
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std::vector<RTLIL::SigBit> pi;
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register_cone(pi, output);
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if (verbose_level >= 1)
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log(" Found %d input signals and %d cells.\n", int(pi.size()), int(ez_cells.size()));
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satgen.setContext(&sigmap, "A");
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int output_a = satgen.importSigSpec(output).front();
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int output_undef_a = satgen.importUndefSigSpec(output).front();
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ez.assume(ez.NOT(ez.expression(ezSAT::OpOr, satgen.importUndefSigSpec(pi))));
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satgen.setContext(&sigmap, "B");
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int output_b = satgen.importSigSpec(output).front();
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int output_undef_b = satgen.importUndefSigSpec(output).front();
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ez.assume(ez.NOT(ez.expression(ezSAT::OpOr, satgen.importUndefSigSpec(pi))));
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for (size_t i = 0; i < pi.size(); i++)
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{
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RTLIL::SigSpec test_sig(pi[i]);
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RTLIL::SigSpec rest_sig(pi);
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rest_sig.remove(i, 1);
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int test_sig_a, test_sig_b;
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std::vector<int> rest_sig_a, rest_sig_b;
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satgen.setContext(&sigmap, "A");
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test_sig_a = satgen.importSigSpec(test_sig).front();
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rest_sig_a = satgen.importSigSpec(rest_sig);
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satgen.setContext(&sigmap, "B");
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test_sig_b = satgen.importSigSpec(test_sig).front();
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rest_sig_b = satgen.importSigSpec(rest_sig);
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if (ez.solve(ez.vec_eq(rest_sig_a, rest_sig_b), ez.XOR(output_a, output_b), ez.XOR(test_sig_a, test_sig_b), ez.NOT(output_undef_a), ez.NOT(output_undef_b))) {
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if (verbose_level >= 2)
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log(" Result for input %s: pass\n", log_signal(test_sig));
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reduced_inputs.push_back(pi[i]);
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} else {
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if (verbose_level >= 2)
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log(" Result for input %s: strip\n", log_signal(test_sig));
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}
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}
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if (verbose_level >= 1)
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log(" Reduced input cone contains %d inputs.\n", int(reduced_inputs.size()));
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}
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};
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struct PerformReduction
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{
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SigMap &sigmap;
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drivers_t &drivers;
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ezDefaultSAT ez;
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SatGen satgen;
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std::vector<int> sat_pi, sat_out, sat_def;
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std::vector<RTLIL::SigBit> out_bits, pi_bits;
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std::vector<bool> out_inverted;
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std::vector<int> out_depth;
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int register_cone_worker(std::set<RTLIL::Cell*> &celldone, std::map<RTLIL::SigBit, int> &sigdepth, RTLIL::SigBit out)
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{
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if (out.wire == NULL)
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return 0;
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if (sigdepth.count(out) != 0)
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return sigdepth.at(out);
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sigdepth[out] = 0;
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if (drivers.count(out) != 0) {
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std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> &drv = drivers.at(out);
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if (celldone.count(drv.first) == 0) {
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if (!satgen.importCell(drv.first))
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log_error("Can't create SAT model for cell %s (%s)!\n", RTLIL::id2cstr(drv.first->name), RTLIL::id2cstr(drv.first->type));
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celldone.insert(drv.first);
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}
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int max_child_dept = 0;
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for (auto &bit : drv.second)
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max_child_dept = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_dept);
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sigdepth[out] = max_child_dept + 1;
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} else {
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pi_bits.push_back(out);
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sat_pi.push_back(satgen.importSigSpec(out).front());
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ez.assume(ez.NOT(satgen.importUndefSigSpec(out).front()));
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}
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return sigdepth[out];
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}
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PerformReduction(SigMap &sigmap, drivers_t &drivers, std::vector<RTLIL::SigBit> &bits) :
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sigmap(sigmap), drivers(drivers), satgen(&ez, &sigmap), out_bits(bits)
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{
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satgen.model_undef = true;
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std::set<RTLIL::Cell*> celldone;
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std::map<RTLIL::SigBit, int> sigdepth;
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for (auto &bit : bits) {
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out_depth.push_back(register_cone_worker(celldone, sigdepth, bit));
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sat_out.push_back(satgen.importSigSpec(bit).front());
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sat_def.push_back(ez.NOT(satgen.importUndefSigSpec(bit).front()));
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}
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if (noinv_mode) {
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out_inverted = std::vector<bool>(sat_out.size(), false);
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} else {
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if (!ez.solve(sat_out, out_inverted, ez.expression(ezSAT::OpAnd, sat_def)))
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log_error("Solving for initial model failed!\n");
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for (size_t i = 0; i < sat_out.size(); i++)
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if (out_inverted.at(i))
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sat_out[i] = ez.NOT(sat_out[i]);
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}
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results, std::vector<int> &bucket, int level)
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{
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if (bucket.size() <= 1)
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return;
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if (verbose_level >= 1)
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log("%*s Trying to shatter bucket with %d signals.\n", 2*level, "", int(bucket.size()));
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std::vector<int> sat_list, sat_inv_list;
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for (int idx : bucket) {
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sat_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_inv_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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}
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std::vector<int> modelVars = sat_out;
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std::vector<bool> model;
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if (verbose_level >= 2) {
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modelVars.insert(modelVars.end(), sat_def.begin(), sat_def.end());
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modelVars.insert(modelVars.end(), sat_pi.begin(), sat_pi.end());
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}
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if (ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_list), ez.expression(ezSAT::OpOr, sat_inv_list)))
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{
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if (verbose_level >= 2) {
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for (size_t i = 0; i < pi_bits.size(); i++)
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log("%*s -> PI %c == %s\n", 2*level, "", model[2*sat_out.size() + i] ? '1' : '0', log_signal(pi_bits[i]));
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for (int idx : bucket)
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log("%*s -> OUT %c == %s%s\n", 2*level, "", model[sat_out.size() + idx] ? model[idx] ? '1' : '0' : 'x',
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out_inverted.at(idx) ? "~" : "", log_signal(out_bits[idx]));
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}
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std::vector<int> buckets[2];
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for (int idx : bucket)
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buckets[model[idx] ? 1 : 0].push_back(idx);
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analyze(results, buckets[0], level+1);
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analyze(results, buckets[1], level+1);
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}
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else
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{
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if (verbose_level >= 1) {
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log("%*s Found %d equivialent signals:", 2*level, "", int(bucket.size()));
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for (int idx : bucket)
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log("%s%s%s", idx == bucket.front() ? " " : ", ", out_inverted[idx] ? "~" : "", log_signal(out_bits[idx]));
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log("\n");
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}
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std::vector<equiv_bit_t> result;
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for (int idx : bucket) {
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equiv_bit_t bit;
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bit.depth = out_depth[idx];
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bit.inverted = out_inverted[idx];
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bit.bit = out_bits[idx];
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result.push_back(bit);
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}
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std::sort(result.begin(), result.end());
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if (result.front().inverted)
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for (auto &bit : result)
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bit.inverted = !bit.inverted;
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results.push_back(result);
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}
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}
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void analyze(std::vector<std::vector<equiv_bit_t>> &results)
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{
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std::vector<int> bucket;
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for (size_t i = 0; i < sat_out.size(); i++)
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bucket.push_back(i);
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analyze(results, bucket, 1);
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}
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};
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struct FreduceHelper
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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bool try_mode;
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ezDefaultSAT ez;
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SigMap sigmap;
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CellTypes ct;
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SatGen satgen;
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ConstEval ce;
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drivers_t drivers;
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SigPool inputs, nodes;
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RTLIL::SigSpec input_sigs;
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SigSet<RTLIL::SigSpec> source_signals;
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std::vector<RTLIL::Const> test_vectors;
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std::map<RTLIL::SigSpec, RTLIL::Const> node_to_data;
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std::map<RTLIL::SigSpec, RTLIL::SigSpec> node_result;
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uint32_t xorshift32_state;
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uint32_t xorshift32() {
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xorshift32_state ^= xorshift32_state << 13;
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xorshift32_state ^= xorshift32_state >> 17;
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xorshift32_state ^= xorshift32_state << 5;
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return xorshift32_state;
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FreduceHelper(RTLIL::Module *module) : module(module), sigmap(module)
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{
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}
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FreduceHelper(RTLIL::Design *design, RTLIL::Module *module, bool try_mode) :
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design(design), module(module), try_mode(try_mode),
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sigmap(module), satgen(&ez, design, &sigmap), ce(module)
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int run()
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{
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log("Running functional reduction on module %s:\n", RTLIL::id2cstr(module->name));
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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xorshift32_state = 123456789;
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xorshift32();
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xorshift32();
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xorshift32();
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}
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bool run_test(RTLIL::SigSpec test_vec)
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{
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ce.clear();
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ce.set(input_sigs, test_vec.as_const());
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for (auto &bit : nodes.bits) {
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RTLIL::SigSpec nodesig(bit.first, 1, bit.second), nodeval = nodesig;
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if (!ce.eval(nodeval)) {
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if (!try_mode)
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log_error("Evaluation of node %s failed!\n", log_signal(nodesig));
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log("FAILED: Evaluation of node %s failed!\n", log_signal(nodesig));
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return false;
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std::vector<std::set<RTLIL::SigBit>> batches;
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for (auto &it : module->cells)
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if (ct.cell_known(it.second->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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for (auto &port : it.second->connections) {
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std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
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if (ct.cell_output(it.second->type, port.first))
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outputs.insert(bits.begin(), bits.end());
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else
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inputs.insert(bits.begin(), bits.end());
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}
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std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
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for (auto &bit : outputs)
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drivers[bit] = drv;
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batches.push_back(outputs);
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}
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node_to_data[nodesig].bits.push_back(nodeval.as_const().bits.at(0));
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}
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return true;
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}
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void dump_node_data()
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{
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int max_node_len = 20;
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for (auto &it : node_to_data)
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max_node_len = std::max(max_node_len, int(strlen(log_signal(it.first))));
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log(" full node fingerprints:\n");
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for (auto &it : node_to_data)
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log(" %-*s %s\n", max_node_len+5, log_signal(it.first), log_signal(it.second));
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}
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bool check(RTLIL::SigSpec sig1, RTLIL::SigSpec sig2)
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{
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log(" performing SAT proof: %s == %s ->", log_signal(sig1), log_signal(sig2));
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std::vector<int> vec1 = satgen.importSigSpec(sig1);
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std::vector<int> vec2 = satgen.importSigSpec(sig2);
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std::vector<int> model = satgen.importSigSpec(input_sigs);
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std::vector<bool> testvect;
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if (ez.solve(model, testvect, ez.vec_ne(vec1, vec2))) {
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RTLIL::SigSpec testvect_sig;
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for (int i = 0; i < input_sigs.width; i++)
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testvect_sig.append(testvect.at(i) ? RTLIL::State::S1 : RTLIL::State::S0);
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testvect_sig.optimize();
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log(" failed: %s\n", log_signal(testvect_sig));
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test_vectors.push_back(testvect_sig.as_const());
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if (!run_test(testvect_sig))
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return false;
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} else {
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log(" success.\n");
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if (!sig1.is_fully_const())
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node_result[sig1].append(sig2);
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if (!sig2.is_fully_const())
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node_result[sig2].append(sig1);
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}
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return true;
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}
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bool analyze_const()
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{
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for (auto &it : node_to_data)
|
||||
int bits_count = 0;
|
||||
std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets;
|
||||
for (auto &batch : batches)
|
||||
{
|
||||
if (node_result.count(it.first))
|
||||
continue;
|
||||
if (it.second == RTLIL::Const(RTLIL::State::S0, it.second.bits.size()))
|
||||
if (!check(it.first, RTLIL::SigSpec(RTLIL::State::S0)))
|
||||
return false;
|
||||
if (it.second == RTLIL::Const(RTLIL::State::S1, it.second.bits.size()))
|
||||
if (!check(it.first, RTLIL::SigSpec(RTLIL::State::S1)))
|
||||
return false;
|
||||
RTLIL::SigSpec batch_sig(std::vector<RTLIL::SigBit>(batch.begin(), batch.end()));
|
||||
batch_sig.optimize();
|
||||
|
||||
log(" Finding reduced input cone for signal batch %s%c\n", log_signal(batch_sig), verbose_level ? ':' : '.');
|
||||
|
||||
FindReducedInputs infinder(sigmap, drivers);
|
||||
for (auto &bit : batch) {
|
||||
std::vector<RTLIL::SigBit> inputs;
|
||||
infinder.analyze(inputs, bit);
|
||||
buckets[inputs].push_back(bit);
|
||||
bits_count++;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
log(" Sorted %d signal bits into %d buckets.\n", bits_count, int(buckets.size()));
|
||||
|
||||
bool analyze_alias()
|
||||
{
|
||||
restart:
|
||||
std::map<RTLIL::Const, RTLIL::SigSpec> reverse_map;
|
||||
|
||||
for (auto &it : node_to_data) {
|
||||
if (node_result.count(it.first) && node_result.at(it.first).is_fully_const())
|
||||
continue;
|
||||
reverse_map[it.second].append(it.first);
|
||||
}
|
||||
|
||||
for (auto &it : reverse_map)
|
||||
std::vector<std::vector<equiv_bit_t>> equiv;
|
||||
for (auto &bucket : buckets)
|
||||
{
|
||||
if (it.second.width <= 1)
|
||||
if (bucket.second.size() == 1)
|
||||
continue;
|
||||
|
||||
it.second.expand();
|
||||
for (int i = 0; i < it.second.width; i++)
|
||||
for (int j = i+1; j < it.second.width; j++) {
|
||||
RTLIL::SigSpec sig1 = it.second.chunks.at(i), sig2 = it.second.chunks.at(j);
|
||||
if (node_result.count(sig1) && node_result.count(sig2))
|
||||
RTLIL::SigSpec bucket_sig(bucket.second);
|
||||
bucket_sig.optimize();
|
||||
|
||||
log(" Trying to shatter bucket %s%c\n", log_signal(bucket_sig), verbose_level ? ':' : '.');
|
||||
PerformReduction worker(sigmap, drivers, bucket.second);
|
||||
worker.analyze(equiv);
|
||||
}
|
||||
|
||||
log(" Rewiring %d equivialent groups:\n", int(equiv.size()));
|
||||
int rewired_sigbits = 0;
|
||||
for (auto &grp : equiv)
|
||||
{
|
||||
log(" Using as master for group: %s\n", log_signal(grp.front().bit));
|
||||
|
||||
RTLIL::SigSpec inv_sig;
|
||||
for (size_t i = 1; i < grp.size(); i++)
|
||||
{
|
||||
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
|
||||
|
||||
if (grp[i].inverted && drv->type == "$_INV_" && sigmap(drv->connections.at("\\A")) == grp[0].bit) {
|
||||
log(" Skipping inverted slave %s: already in reduced form\n", log_signal(grp[i].bit));
|
||||
continue;
|
||||
if (node_to_data.at(sig1) != node_to_data.at(sig2))
|
||||
goto restart;
|
||||
if (!check(it.second.chunks.at(i), it.second.chunks.at(j)))
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool toproot_helper(RTLIL::SigSpec cursor, RTLIL::SigSpec stoplist, RTLIL::SigSpec &donelist, int level)
|
||||
{
|
||||
// log(" %*schecking %s: %s\n", level*2, "", log_signal(cursor), log_signal(stoplist));
|
||||
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
|
||||
|
||||
if (stoplist.extract(cursor).width != 0) {
|
||||
// log(" %*s STOP\n", level*2, "");
|
||||
return false;
|
||||
}
|
||||
RTLIL::Wire *dummy_wire = module->new_wire(1, NEW_ID);
|
||||
for (auto &port : drv->connections) {
|
||||
RTLIL::SigSpec mapped = sigmap(port.second);
|
||||
mapped.replace(grp[i].bit, dummy_wire, &port.second);
|
||||
}
|
||||
|
||||
if (donelist.extract(cursor).width != 0)
|
||||
return true;
|
||||
if (grp[i].inverted)
|
||||
{
|
||||
if (inv_sig.width == 0)
|
||||
{
|
||||
inv_sig = module->new_wire(1, NEW_ID);
|
||||
|
||||
stoplist.append(cursor);
|
||||
std::set<RTLIL::SigSpec> next = source_signals.find(cursor);
|
||||
|
||||
for (auto &it : next)
|
||||
if (!toproot_helper(it, stoplist, donelist, level+1))
|
||||
return false;
|
||||
|
||||
donelist.append(cursor);
|
||||
return true;
|
||||
}
|
||||
|
||||
// KISS topological sort of bits in signal. return one element of sig
|
||||
// without dependencies to the others (or empty if input is not a DAG).
|
||||
RTLIL::SigSpec toproot(RTLIL::SigSpec sig)
|
||||
{
|
||||
sig.expand();
|
||||
// log(" finding topological root in %s:\n", log_signal(sig));
|
||||
for (auto &c : sig.chunks) {
|
||||
RTLIL::SigSpec stoplist = sig, donelist;
|
||||
stoplist.remove(c);
|
||||
// log(" testing %s as root:\n", log_signal(c));
|
||||
if (toproot_helper(c, stoplist, donelist, 0))
|
||||
return c;
|
||||
}
|
||||
return RTLIL::SigSpec();
|
||||
}
|
||||
|
||||
void update_design_for_group(RTLIL::SigSpec root, RTLIL::SigSpec rest)
|
||||
{
|
||||
SigPool unlink;
|
||||
unlink.add(rest);
|
||||
|
||||
for (auto &cell_it : module->cells) {
|
||||
RTLIL::Cell *cell = cell_it.second;
|
||||
if (!ct.cell_known(cell->type))
|
||||
continue;
|
||||
for (auto &conn : cell->connections)
|
||||
if (ct.cell_output(cell->type, conn.first)) {
|
||||
RTLIL::SigSpec sig = sigmap(conn.second);
|
||||
sig.expand();
|
||||
bool did_something = false;
|
||||
for (auto &c : sig.chunks) {
|
||||
if (c.wire == NULL || !unlink.check_any(c))
|
||||
continue;
|
||||
c.wire = new RTLIL::Wire;
|
||||
c.wire->name = NEW_ID;
|
||||
module->add(c.wire);
|
||||
assert(c.width == 1);
|
||||
c.offset = 0;
|
||||
did_something = true;
|
||||
RTLIL::Cell *inv_cell = new RTLIL::Cell;
|
||||
inv_cell->name = NEW_ID;
|
||||
inv_cell->type = "$_INV_";
|
||||
inv_cell->connections["\\A"] = grp[0].bit;
|
||||
inv_cell->connections["\\Y"] = inv_sig;
|
||||
module->add(inv_cell);
|
||||
}
|
||||
if (did_something) {
|
||||
sig.optimize();
|
||||
conn.second = sig;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rest.expand();
|
||||
for (auto &c : rest.chunks) {
|
||||
if (c.wire != NULL && !root.is_fully_const()) {
|
||||
source_signals.erase(c);
|
||||
source_signals.insert(c, root);
|
||||
module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));
|
||||
}
|
||||
else
|
||||
module->connections.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit));
|
||||
|
||||
rewired_sigbits++;
|
||||
}
|
||||
module->connections.push_back(RTLIL::SigSig(c, root));
|
||||
}
|
||||
}
|
||||
|
||||
void analyze_groups()
|
||||
{
|
||||
SigMap to_group_major;
|
||||
for (auto &it : node_result) {
|
||||
it.second.expand();
|
||||
for (auto &c : it.second.chunks)
|
||||
to_group_major.add(it.first, c);
|
||||
}
|
||||
|
||||
std::map<RTLIL::SigSpec, RTLIL::SigSpec> major_to_rest;
|
||||
for (auto &it : node_result)
|
||||
major_to_rest[to_group_major(it.first)].append(it.first);
|
||||
|
||||
for (auto &it : major_to_rest)
|
||||
{
|
||||
RTLIL::SigSig group = it;
|
||||
|
||||
if (!it.first.is_fully_const()) {
|
||||
group.first = toproot(it.second);
|
||||
if (group.first.width == 0) {
|
||||
log("Operating on non-DAG input: failed to find topological root for `%s'.\n", log_signal(it.second));
|
||||
return;
|
||||
}
|
||||
group.second.remove(group.first);
|
||||
}
|
||||
|
||||
group.first.optimize();
|
||||
group.second.sort_and_unify();
|
||||
|
||||
log(" found group: %s -> %s\n", log_signal(group.first), log_signal(group.second));
|
||||
update_design_for_group(group.first, group.second);
|
||||
}
|
||||
}
|
||||
|
||||
void run()
|
||||
{
|
||||
log("\nFunctionally reduce module %s:\n", RTLIL::id2cstr(module->name));
|
||||
|
||||
// find inputs and nodes (nets driven by internal cells)
|
||||
// add all internal cells to sat solver
|
||||
|
||||
for (auto &cell_it : module->cells) {
|
||||
RTLIL::Cell *cell = cell_it.second;
|
||||
if (!ct.cell_known(cell->type))
|
||||
continue;
|
||||
RTLIL::SigSpec cell_inputs, cell_outputs;
|
||||
for (auto &conn : cell->connections)
|
||||
if (ct.cell_output(cell->type, conn.first)) {
|
||||
nodes.add(sigmap(conn.second));
|
||||
cell_outputs.append(sigmap(conn.second));
|
||||
} else {
|
||||
inputs.add(sigmap(conn.second));
|
||||
cell_inputs.append(sigmap(conn.second));
|
||||
}
|
||||
cell_inputs.sort_and_unify();
|
||||
cell_outputs.sort_and_unify();
|
||||
cell_inputs.expand();
|
||||
for (auto &c : cell_inputs.chunks)
|
||||
if (c.wire != NULL)
|
||||
source_signals.insert(cell_outputs, c);
|
||||
if (!satgen.importCell(cell))
|
||||
log_error("Failed to import cell to SAT solver: %s (%s)\n",
|
||||
RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
|
||||
}
|
||||
inputs.del(nodes);
|
||||
nodes.add(inputs);
|
||||
log(" found %d nodes (%d inputs).\n", int(nodes.size()), int(inputs.size()));
|
||||
|
||||
// initialise input_sigs and add all-zero, all-one and a few random test vectors
|
||||
|
||||
input_sigs = inputs.export_all();
|
||||
test_vectors.push_back(RTLIL::SigSpec(RTLIL::State::S0, input_sigs.width).as_const());
|
||||
test_vectors.push_back(RTLIL::SigSpec(RTLIL::State::S1, input_sigs.width).as_const());
|
||||
|
||||
for (int i = 0; i < NUM_INITIAL_RANDOM_TEST_VECTORS; i++) {
|
||||
RTLIL::SigSpec sig;
|
||||
for (int j = 0; j < input_sigs.width; j++)
|
||||
sig.append(xorshift32() % 2 ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
sig.optimize();
|
||||
assert(sig.width == input_sigs.width);
|
||||
test_vectors.push_back(sig.as_const());
|
||||
}
|
||||
|
||||
for (auto &test_vec : test_vectors)
|
||||
if (!run_test(test_vec))
|
||||
return;
|
||||
|
||||
// run the analysis and update design
|
||||
|
||||
if (!analyze_const())
|
||||
return;
|
||||
|
||||
if (!analyze_alias())
|
||||
return;
|
||||
|
||||
log(" input vector: %s\n", log_signal(input_sigs));
|
||||
for (auto &test_vec : test_vectors)
|
||||
log(" test vector: %s\n", log_signal(test_vec));
|
||||
|
||||
dump_node_data();
|
||||
analyze_groups();
|
||||
log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name));
|
||||
return rewired_sigbits;
|
||||
}
|
||||
};
|
||||
|
||||
|
|
@ -376,41 +425,46 @@ struct FreducePass : public Pass {
|
|||
log("equivialent, they are merged to one node and one of the redundant drivers is\n");
|
||||
log("removed.\n");
|
||||
log("\n");
|
||||
log(" -try\n");
|
||||
log(" do not issue an error when the analysis fails.\n");
|
||||
log(" (usually beacause of logic loops in the design)\n");
|
||||
log(" -v, -vv\n");
|
||||
log(" enable verbose or very verbose output\n");
|
||||
log("\n");
|
||||
log(" -noinv\n");
|
||||
log(" do not consolidate inverted signals\n");
|
||||
log("\n");
|
||||
// log(" -enable_invert\n");
|
||||
// log(" also detect nodes that are inverse to each other.\n");
|
||||
// log("\n");
|
||||
}
|
||||
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
bool enable_invert = false;
|
||||
bool try_mode = false;
|
||||
verbose_level = 0;
|
||||
noinv_mode = false;
|
||||
|
||||
log_header("Executing FREDUCE pass (perform functional reduction).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-enable_invert") {
|
||||
enable_invert = true;
|
||||
if (args[argidx] == "-v") {
|
||||
verbose_level = 1;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-try") {
|
||||
try_mode = true;
|
||||
if (args[argidx] == "-vv") {
|
||||
verbose_level = 2;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noinv") {
|
||||
noinv_mode = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto &mod_it : design->modules)
|
||||
{
|
||||
int bitcount = 0;
|
||||
for (auto &mod_it : design->modules) {
|
||||
RTLIL::Module *module = mod_it.second;
|
||||
if (design->selected(module))
|
||||
FreduceHelper(design, module, try_mode).run();
|
||||
bitcount += FreduceHelper(module).run();
|
||||
}
|
||||
|
||||
log("Rewired a total of %d signal bits.\n", bitcount);
|
||||
}
|
||||
} FreducePass;
|
||||
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ struct SatHelper
|
|||
bool gotTimeout;
|
||||
|
||||
SatHelper(RTLIL::Design *design, RTLIL::Module *module, bool enable_undef) :
|
||||
design(design), module(module), sigmap(module), ct(design), satgen(&ez, design, &sigmap)
|
||||
design(design), module(module), sigmap(module), ct(design), satgen(&ez, &sigmap)
|
||||
{
|
||||
this->enable_undef = enable_undef;
|
||||
satgen.model_undef = enable_undef;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue